參數(shù)資料
型號(hào): PSD835G1V-C-12MI
廠商: 意法半導(dǎo)體
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述: 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
文件頁數(shù): 46/110頁
文件大?。?/td> 570K
代理商: PSD835G1V-C-12MI
PSD835G2
PSD8XX Family
45
The
PSD835G2
Functional
Blocks
(cont.)
9.3.3 Microcontroller Interface Examples
Figures 19 through 23 show examples of the basic connections between the PSD835G2
and some popular microcontrollers. The PSD835G2 Control input pins are labeled as to
the microcontroller function for which they are configured. The MCU interface is specified
using the PSDsoft.
9.3.3.1 80C31
Figure 19 shows the interface to the 80C31, which has an 8-bit multiplexed address/data
bus. The lower address byte is multiplexed with the data bus. The microcontroller control
signals PSEN, RD, and WR may be used for accessing the internal memory components
and I/O Ports. The ALE input (pin PD0) latches the address.
9.3.3.2 80C251
The Intel 80C251 microcontroller features a user-configurable bus interface with four
possible bus configurations, as shown in Table 15.
Configuration 1 is 80C31 compatible, and the bus interface to the PSD835G2 is identical to
that shown in Figure 19. Configurations 2 and 3 have the same bus connection as shown
in Figure 20. There is only one read input (PSEN) connected to the Cntl1 pin on the
PSD835G2. The A16 connection to the PA0 pin allows for a larger address input to the
PSD835G2. Configuration 4 is shown in Figure 21. The RD signal is connected to Cntl1
and the PSEN signal is connected to the CNTL2.
The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In
Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in
every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus
cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0]
are changing. The PSD835G2 supports both modes. In Page Mode, the PSD bus timing
is identical to Non-Page Mode except the address hold time and setup time with respect
to ALE is not required. The PSD access time is measured from address A[7:0] valid to
data in valid.
相關(guān)PDF資料
PDF描述
PSD835G1V-C-12U Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G1V-C-70JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G1V-C-70M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G1V-C-70MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G1V-C-70U Configurable Memory System on a Chip for 8-Bit Microcontrollers
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