- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368241 > PSD835F3V-C-12B81I (意法半導(dǎo)體) Configurable Memory System on a Chip for 8-Bit Microcontrollers PDF資料下載
參數(shù)資料
| 型號： | PSD835F3V-C-12B81I |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存儲系統(tǒng) |
| 文件頁數(shù)： | 72/110頁 |
| 文件大?。?/td> | 570K |
| 代理商： | PSD835F3V-C-12B81I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當前第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁
PSD835G2
PSD8XX Family
71
9.6.1 Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three
different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are
inputs, waiting for a serial command from an external JTAG controller device (such as
FlashLink or Automated Test Equipment). When the enabling command is received from
the external JTAG controller, TDO becomes an output and the JTAG channel is fully
functional inside the PSD. The same command that enables the JTAG channel may
optionally enable the two additional JTAG pins, TSTAT and TERR.
The following symbolic logic equation specifies the conditions enabling the four basic
JTAG pins (TMS, TCK, TDI, and TDO) on their respective Port E pins. For purposes of
discussion, the logic label JTAG_ON will be used. When JTAG_ON is true, the four pins
are enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD
I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside the PSD is set by the designer
in the PSDsoft Configuration utility. This dedicates the pins for
JTAG at all times (compliant with IEEE 1149.1) */
Microcontroller_enabled +
/* The microcontroller can set a bit at run-time by writing to the
PSD register, JTAG Enable. This register is located at address
CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this
register will enable the pins for JTAG use. This bit is cleared
by a PSD reset or the microcontroller. See Table 31 for bit
definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside the PSD can be used to
enable the JTAG pins. This PT has the reserved name
JTAGSEL. Once defined as a node in PSDabel, the designer
can write an equation for JTAGSEL. This method is used when
the Port E JTAG pins are multiplexed with other I/O signals.
It is recommended to logically tie the node JTAGSEL to the
JEN\ signal on the Flashlink cable when multiplexing JTAG
signals. See Application Note 54 for details.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
*
*
*
JTAG_ENABLE
Table 31. JTAG Enable Register
JTAG Enable
*
Bits 1-7 are not used and should set to 0.
Bit definitions:
JTAG_ENABLE 1 = JTAG Port is Enabled.
0 = JTAG Port is Disabled.
NOTE:
The state of the PSD reset input signal will not interrupt (or prevent) JTAG operations if
the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft). However, the
PSD reset input will prevent or interrupt JTAG operations if the JTAG enable register is
used to enable the JTAG pins.
The
PSD835G2
Functional
Blocks
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD835F3V-C-12J | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F3V-C-12JI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F3V-C-12M | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F3V-C-12MI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F3V-C-12U | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD835G2-70U | 功能描述:靜態(tài)隨機存取存儲器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2-90U | 功能描述:靜態(tài)隨機存取存儲器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2-90UI | 功能描述:靜態(tài)隨機存取存儲器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2V-12UI | 功能描述:靜態(tài)隨機存取存儲器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2V-90U | 功能描述:靜態(tài)隨機存取存儲器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。