參數(shù)資料
      

      


      


      
型號(hào)：
PSD835F2V-C-15UI

      

      
廠商：
意法半導(dǎo)體

      

      
英文描述：
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      
中文描述：
在8片位微控制器可配置存儲(chǔ)系統(tǒng)

      

      
文件頁(yè)數(shù)：
69/110頁(yè)

      

      
文件大?。?/td>
570K

      

      
代理商：
PSD835F2V-C-15UI


      

      

      

	
      
    
    

    
      
	
      PSD8XX Family 
      PSD835G2
      68
      APD
      ALE
      Enable Bit
      0
      1
      1
      1
      PD Polarity
      X
      X
      1
      0
      ALE Level
      X
      Pulsing
      1
      0
      APD Counter
      Not Counting
      Not Counting
      Counting (Generates PDN after 15 Clocks)
      Counting (Generates PDN after 15 Clocks)
      Table 28.  APD Counter Operation
      The 
      PSD835G2
      Functional
      Blocks
      (cont.)
      9.5.2   Other Power Saving Options
      The PSD835G2 offers other reduced power saving options that are independent of the 
      Power Down Mode. Except for the SRAM Standby and CSI input features, they are
      enabled by setting bits in the PMMR0 and PMMR2 registers.
      9.5.2.1   Zero Power PLD
      The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. 
      By setting the bit to “1”, the Turbo mode is disabled and the PLDs consume Zero Power
      current when the inputs are not switching for an extended time of 70 ns. The propagation
      delay time will be increased after the Turbo bit is set to “1” (turned off) when the inputs
      change at a composite frequency of less than 15 MHz. When the Turbo bit is set to a “0”
      (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD’s D.C.
      power, AC power, and propagation delay. Refer to AC/DC spec for PLD timings.
      Note:
       Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power
      consumption.
      9.5.2.2   SRAM Standby Mode (Battery Backup)
      The PSD835G2 supports a battery backup operation that retains the contents of the SRAM 
      in the event of a power loss. The SRAM has a Vstby pin (PE6) that can be connected to
      an external battery. When V
      CC
      becomes lower than Vstby then the PSD will automatically
      connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is
      typically 0.5 μA. The SRAM data retention voltage is 2 V minimum. The battery-on 
      indicator (Vbaton) can be routed to PE7. This signal indicates when the V
      CC
      has dropped
      below the Vstby voltage and that the SRAM is running on battery power. 
      9.5.2.3   The CSI Input
      Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal 
      selects and enables the internal Flash, Boot Block, SRAM, and I/O for read or write 
      operations involving the PSD835G2. A high on the CSI pin will disable the Flash memory,
      Boot Block, and SRAM, and reduce the PSD power consumption. However, the PLD and
      I/O pins remain operational when CSI is high. 
      Note:
       there may be a timing penalty when
      using the CSI pin depending on the speed grade of the PSD that you are using. See the
      timing parameter t
      SLQV
      in the AC/DC specs.
      9.5.2.4   Input Clock
      The PSD4000 provides the option to turn off the CLKIN input to the PLD to save AC 
      power consumption. The CLKIN is an input to the PLD AND array and the Output
      Micro
      Cells. During Power Down Mode, or, if the CLKIN input is not being used as part of
      the PLD logic equation, the clock should be disabled to save AC power. The CLKIN will be
      disconnected from the PLD AND array or the Micro
      Cells by setting bits 4 or 5 to a “1” in
      PMMR0.
      9.5.2.5   MCU Control Signals
      The PSD835G2 provides the option to turn off the address input (A7-0) and input control 
      signals (CNTL0-2, ALE, and DBE) to the PLD to save AC power consumption. These 
      signals are inputs to the PLD AND array. During Power Down Mode, or, if any of them are
      not being used as part of the PLD logic equation, these control signals should be disabled
      to save AC power. They will be disconnected from the PLD AND array by setting bits 0, 2,
      3, 4, 5, and 6 to a “1” in the PMMR2.
      
    
      
    
    
      


      


      

      相關(guān)PDF資料
      		

      PDF描述
      		

      
      

      
PSD835F2V-C-20B81
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      
PSD835F2V-C-20B81I
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      
PSD835F2V-C-20J
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      
PSD835F2V-C-90UI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      
PSD835F3-70U
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      

      

      


      


      

      相關(guān)代理商/技術(shù)參數(shù)
      		

      參數(shù)描述
      		

      
      

      
PSD835G2-70U
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

      

      
PSD835G2-90U
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

      

      
PSD835G2-90UI
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

      

      
PSD835G2V-12UI
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 120ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

      

      
PSD835G2V-90U
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 90ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

      

      
    
    
    
	
      	
    
    
     
     
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