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    參數(shù)資料
    型號(hào): PSD835F2V-A-70M
    廠商: 意法半導(dǎo)體
    英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
    中文描述: 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
    文件頁數(shù): 70/110頁
    文件大?。?/td> 570K
    代理商: PSD835F2V-A-70M
    PSD835G2
    PSD8XX Family
    69
    The
    PSD835G2
    Functional
    Blocks
    (cont.)
    9.5.3 Reset and Power On Requirement
    9.5.3.1 Power On Reset
    Upon power up the PSD835G2 requires a reset pulse of tNLNH-PO (minimum 1 ms) after
    V
    CC
    is steady. During this time period the device loads internal configurations, clears
    some of the registers and sets the Flash into operating mode. After the rising edge of
    reset, the PSD835G2 remains in the reset state for an additional tOPR (maximum 120 ns)
    nanoseconds before the first memory access is allowed.
    The PSD835G2 Flash memory is reset to the read array mode upon power up. The FSi
    and CSBOOTi select signals along with the write strobe signal must be in the false
    state during power-up reset for maximum security of the data contents and to remove
    the possibility of data being written on the first edge of a write strobe signal. Any Flash
    memory write cycle initiation is prevented automatically when V
    CC
    is below VLKO.
    9.5.3.2 Warm Reset
    Once the device is up and running, the device can be reset with a much shorter pulse of
    tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
    after warm reset. Figure 31 shows the timing of the power on and warm reset.
    OPERATING LEVEL
    POWER ON RESET
    V
    CC
    RESET
    tNLNH
    PO
    tOPR
    tNLNH-A
    tNLNH
    tOPR
    WARM
    RESET
    Figure 31. Power On and Warm Reset Timing
    9.5.3.3
    I/OPin, Register and PLD Status at Reset
    Table 29 shows the I/O pin, register and PLD status during power on reset, warm reset
    and power down mode. PLD outputs are always valid during warm reset, and they are
    valid in power on reset once the internal PSD configuration bits are loaded. This loading of
    PSD is completed typically long before the V
    CC
    ramps up to operating level. Once the PLD
    is active, the state of the outputs are determined by the equations specified in PSDsoft.
    相關(guān)PDF資料
    PDF描述
    PSD835F2V-A-70MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F2V-A-70U Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F2V-A-70UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F2V-A-90B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F2V-A-90B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
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