參數(shù)資料
型號(hào)： PSD835F2V-70B81I
廠商： 意法半導(dǎo)體
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
文件頁(yè)數(shù)： 59/110頁(yè)
文件大?。?/td> 570K
代理商： PSD835F2V-70B81I
PSD8XX Family
PSD835G2
58
The
PSD835G2
Functional
Blocks
(cont.)
9.4.3.1 Control Register
Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode,
and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports E, F and
G have an associated Control Register.
9.4.3.2 Direction Register
The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to ‘1’
in the Direction Register will cause the corresponding pin to be an output, and any bit set
to ‘0’ will cause it to be an input. The default mode for all port pins is input.
Figures 26 and 28 show the Port Architecture diagrams for Ports A/B/C and E/F/G
respectively. The direction of data flow for Ports A, B, C and F are controlled not only by
the direction register, but also by the output enable product term from the PLD AND array.
If the output enable product term is not active, the Direction Register has sole control of a
given pin’s direction.
An example of a configuration for a port with the three least significant bits set to output
and the remainder set to input is shown in Table 22. Since Port D only contains four pins,
the Direction Register for Port D has only the four least significant bits active.
Direction Register Bit
0
1
Port Pin Mode
Input
Output
Table 20. Port Pin Direction Control,
Output Enable P.T. Not Defined
Direction Register Bit
0
0
1
1
Output Enable P.T.
0
1
0
1
Port Pin Mode
Input
Output
Output
Output
Table 21. Port Pin Direction Control, Output Enable P.T. Defined
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
Table 22. Port Direction Assignment Example
相關(guān)PDF資料
PDF描述
PSD835F2V-70J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F2V-70JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F2V-70M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F2V-70MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F2V-70U Configurable Memory System on a Chip for 8-Bit Microcontrollers
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PSD835G2-70U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2-90U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2-90UI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2V-12UI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2V-90U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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