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參數(shù)資料
| 型號： | PSD835F1V-C-70U |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存儲(chǔ)系統(tǒng) |
| 文件頁數(shù)： | 40/110頁 |
| 文件大?。?/td> | 570K |
| 代理商： | PSD835F1V-C-70U |
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PSD835G2
PSD8XX Family
39
9.2.2.2 The Product Term Allocator
The CPLD has a Product Term Allocator. The PSDsoft uses the Allocator to borrow and
place product terms from one Micro
Cell to another. The following list summarizes how
product terms are allocated:
McellA0-7 all have three native product terms and may borrow up to six more
McellB0-3 all have four native product terms and may borrow up to five more
McellB4-7 all have four native product terms and may borrow up to six more.
Each Micro
Cell may only borrow product terms from certain other Micro
Cells. Product
terms already in use by one Micro
Cell will not be available for a different Micro
Cell.
If an equation requires more product terms than what is available to it, then
“
external
”
product terms will be required, which will consume other OMCs. If external product terms
are used, extra delay will be added for the equation that required the extra product terms.
This is called product term expansion. PSDsoft will perform this expansion as needed.
9.2.2.3 Loading and Reading the Output Micro
Cells (OMCs)
The OMCs occupy a memory location in the MCU address space, as defined by the
CSIOP (refer to the I/O section). The flip-flops in each of the 16 OMCs can be loaded from
the data bus by a microcontroller. Loading the OMCs with data from the MCU takes priority
over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be
overridden by the MCU. The ability to load the flip-flops and read them back is useful in
such applications as loadable counters and shift registers, mailboxes, and handshaking
protocols. Data is loaded to the OMCs on the trailing edge of the WR signal .
9.2.2.4 The OMC Mask Register
There is one Mask Register for each of the two groups of eight OMCs. The Mask Registers
can be used to block the loading of data to individual OMCs. The default value for the
Mask Registers is 00h, which allows loading of the OMCs. When a given bit in a Mask
Register is set to a
‘
1
’
, the MCU will be blocked from writing to the associated OMC. For
example, suppose McellA0-3 are being used for a state machine. You would not want a
MCU write to McellA to overwrite the state machine registers. Therefore, you would want to
load the Mask Register for McellA (Mask Micro
Cell A) with the value 0Fh.
9.2.2.5 The Output Enable of the OMC
The OMC can be connected to an I/O port pin as a PLD output. The output enable of each
Port pin driver is controlled by a single product term from the AND array, ORed with the
Direction Register output. The pin is enabled upon power up if no output enable equation
is defined and if the pin is declared as a PLD output in PSDsoft.
If the OMC output is declared as an internal node and not as a Port pin output in the
PSDabel file, then the Port pin can be used for other I/O functions. The internal node
feedback can be routed as an input to the AND array.
The
PSD835G2
Functional
Blocks
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD835F1V-C-70UI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F1V-C-90B81 | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F1V-C-90B81I | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F1V-C-90J | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F1V-C-90JI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD835G2-70U | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2-90U | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2-90UI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2V-12UI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2V-90U | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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