參數(shù)資料
型號: PSD835F1V-A-70MI
廠商: 意法半導(dǎo)體
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述: 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù): 77/110頁
文件大?。?/td> 570K
代理商: PSD835F1V-A-70MI
PSD8XX Family
PSD835G2
76
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
% Flash Access
% SRAM access
% I/O access
Operational Modes
% Normal
% Power Down Mode
Number of product terms used
(from fitter report)
% of total product terms
Turbo Mode
=
=
=
=
=
8 MHz
4 MHz
80%
15%
5% (no additional power above base)
=
=
10%
90%
=
=
=
45 PT
45/193 = 23.3%
Off
Calculation (typical numbers used)
I
CC
total = Ipwrdown x %pwrdown + %normal x
(
I
CC
(ac) + I
CC
(dc)
)
= Ipwrdown x %pwrdown + % normal x
(
%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD)
)
= 50 μA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 24 mA)
= 45 μA + 0.1 x (8 + 0.9 + 24)
= 45 μA + 0.1 x 32.9
= 45 μA + 3.29 mA
= 3.34 mA
This is the operating power with no Flash writes or erases. Calculation is based
on I
OUT
= 0 mA.
Example of Typical Power Calculation at V
CC
= 5.0 V in Turbo Off Mode
AC/DC
Parameters
(cont.)
相關(guān)PDF資料
PDF描述
PSD835F1V-A-70U Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-A-70UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-A-90B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-A-90B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-A-90J Configurable Memory System on a Chip for 8-Bit Microcontrollers
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