參數資料
型號: PSD835F1V-90B81
廠商: 意法半導體
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述: 在8片位微控制器可配置存儲系統(tǒng)
文件頁數: 58/110頁
文件大?。?/td> 570K
代理商: PSD835F1V-90B81
PSD835G2
PSD8XX Family
The
PSD835G2
Functional
Blocks
(cont.)
57
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PF0-PF7
D0-D7
DATA BUS
Figure 25. Peripheral I/OMode
9.4.3 Port Configuration Registers (PCRs)
Each port has a set of PCRs used for configuration. The contents of the registers can be
accessed by the microcontroller through normal read/write bus cycles at the addresses
given in Table 6. The addresses in Table 6 are the offsets in hex from the base of the
CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,
shown in Table 22, are used for setting the port configurations. The default power-up state
for each register in Table 19 is 00h.
Register Name
Port
MCU Access
Control
Direction
Drive Select*
E,F,G
A,B,C,D,E,F,G
A,B,C,D,E,F,G
Write/Read
Write/Read
Write/Read
Table 19. Port Configuration Registers
*
NOTE:
See Table 26 for Drive Register bit definition.
相關PDF資料
PDF描述
PSD835F1V-90B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-90J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-90JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-90M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-90MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
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