參數(shù)資料
型號: PSD835F1V-70U
廠商: 意法半導(dǎo)體
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述: 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù): 103/110頁
文件大?。?/td> 570K
代理商: PSD835F1V-70U
PSD8XX Family
PSD835G2
102
Symbol
Parameter
1
Conditions Typical
2
Max Unit
C
IN
C
OUT
C
VPP
Capacitance (for input pins only)
V
IN
= 0 V
V
OUT
= 0 V
V
PP
= 0 V
4
6
pF
Capacitance (for input/output pins)
8
12
pF
Capacitance (for CNTL2/V
PP
)
18
25
pF
NOTES:
1. These parameters are only sampled and are not 100% tested.
2. Typical values are for T
A
= 25
°
C and nominal supply voltages.
T
A
= 25 °C, f = 1 MHz
14.0
Pin Capacitance
15.0
Figure 46.
AC Testing
Input/Output
Waveform
16.0
Figure 47.
AC Testing
Load Circuit
17.0
Programming
3.0V
0V
TEST POINT
1.5V
DEVICE
UNDER TEST
2.01 V
195
C
L
= 30 pF
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
Upon delivery from ST, the PSD835G2 device has all bits in the PLDs and
memories in the
1
or high state. The configuration bits are in the
0
or low state. The
code, configuration, and PLDs logic are loaded through the procedure of programming.
Information for programming the device is available directly from ST. Please
contact your local sales representative. (See the last page.)
相關(guān)PDF資料
PDF描述
PSD835F1V-70UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-90B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-90B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-90J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-90JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
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