參數(shù)資料
    型號(hào): PSD835F1-A-70J
    廠商: 意法半導(dǎo)體
    英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
    中文描述: 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
    文件頁(yè)數(shù): 62/110頁(yè)
    文件大?。?/td> 570K
    代理商: PSD835F1-A-70J
    PSD835G2
    PSD8XX Family
    61
    9.4.5 Ports A, B and C – Functionality and Structure
    Ports A and B have similar functionality and structure, as shown in Figure 26. The two
    ports can be configured to perform one or more of the following functions:
    J
    MCU I/O Mode
    J
    CPLD Output – Micro
    Cells McellA[7:0] can be connected to Port A.
    McellB[7:0] can be connected to Port B.
    External chip select ECS [7:0] can be connected to Port C.
    J
    CPLD Input
    – Via the input Micro
    Cells.
    J
    Address In – Additional high address inputs using the Input Micro
    Cells.
    J
    Open Drain/Slew Rate – pins PC[7:0]can be configured to fast slew rate,
    pins PA[7:0] and PB[7:0] can be configured to Open Drain
    Mode.
    I
    D
    R
    D
    Q
    D
    Q
    W
    W
    M
    M
    E
    E
    R
    P
    D
    B
    C
    D
    I
    M
    C
    E
    D
    O
    S
    O
    M
    P
    D
    Figure 26. Port A, B and C
    The
    PSD835G2
    Functional
    Blocks
    (cont.)
    相關(guān)PDF資料
    PDF描述
    PSD835F1-A-70JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F1-A-70M Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F1-A-70MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F1-A-70U Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F1-A-70UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
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