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      • 參數(shù)資料
        型號(hào): PSD835F1-12U
        廠商: 意法半導(dǎo)體
        英文描述: High Speed Voltage Mode Pulse Width Modulator 8-PDIP -40 to 85
        中文描述: 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
        文件頁(yè)數(shù): 13/110頁(yè)
        文件大?。?/td> 570K
        代理商: PSD835F1-12U
        PSD8XX Family
        PSD835G2
        12
        Bit 7
        Bit 6
        Bit 5
        Bit 4
        Bit 3
        Bit 2
        Bit 1
        Bit 0
        Port Pin 7
        Port Pin 6
        Port Pin 5
        Port Pin 4
        Port Pin 3
        Port Pin 2
        Port Pin 1
        Port Pin 0
        Data In Registers – Port A, B, C, D, E, F and G
        8.0
        Register Bit
        Definition
        All the registers in the PSD835G2 are included here for reference. Detail description of the
        registers are found in the Functional Block section of the Data Sheet.
        Bit definitions:
        Read only registers, read Port pin status when Port is in MCU I/O input Mode.
        Bit 7
        Bit 6
        Bit 5
        Bit 4
        Bit 3
        Bit 2
        Bit 1
        Bit 0
        Port Pin 7
        Port Pin 6
        Port Pin 5
        Port Pin 4
        Port Pin 3
        Port Pin 2
        Port Pin 1
        Port Pin 0
        Data Out Registers – Port A, B, C, D, E, F and G
        Bit definitions:
        Latched data for output to Port pin when pin is configured in MCU I/O output mode.
        Bit 7
        Bit 6
        Bit 5
        Bit 4
        Bit 3
        Bit 2
        Bit 1
        Bit 0
        Port Pin 7
        Port Pin 6
        Port Pin 5
        Port Pin 4
        Port Pin 3
        Port Pin 2
        Port Pin 1
        Port Pin 0
        Direction Registers – Port A, B, C, D, E, F and G
        Bit definitions:
        Set Register Bit to 0 = configure corresponding Port pin in Input mode (default).
        Set Register Bit to 1 = configure corresponding Port pin in Output mode.
        Bit 7
        Bit 6
        Bit 5
        Bit 4
        Bit 3
        Bit 2
        Bit 1
        Bit 0
        Port Pin 7
        Port Pin 6
        Port Pin 5
        Port Pin 4
        Port Pin 3
        Port Pin 2
        Port Pin 1
        Port Pin 0
        Control Registers – Ports E, F and G
        Bit definitions:
        Set Register Bit to 0 = configure corresponding Port pin in MCU I/O mode (default).
        Set Register Bit to 1 = configure corresponding Port pin in Latched Address Out mode.
        Bit 7
        Bit 6
        Bit 5
        Bit 4
        Bit 3
        Bit 2
        Bit 1
        Bit 0
        Port Pin 7
        Port Pin 6
        Port Pin 5
        Port Pin 4
        Port Pin 3
        Port Pin 2
        Port Pin 1
        Port Pin 0
        Drive Registers – Ports A, B, D, E, and G
        Bit definitions:
        Set Register Bit to 0 = configure corresponding Port pin in CMOS output driver (default).
        Set Register Bit to 1 = configure corresponding Port pin in Open Drain output driver.
        Bit 7
        Bit 6
        Bit 5
        Bit 4
        Bit 3
        Bit 2
        Bit 1
        Bit 0
        Port Pin 7
        Port Pin 6
        Port Pin 5
        Port Pin 4
        Port Pin 3
        Port Pin 2
        Port Pin 1
        Port Pin 0
        Drive Registers – Ports C and F
        Bit definitions:
        Set Register Bit to 0 = configure corresponding Port pin as CMOS output driver (default).
        Set Register Bit to 1 = configure corresponding Port pin in Slew Rate mode.
        Bit 7
        Bit 6
        Bit 5
        Bit 4
        Bit 3
        Bit 2
        Bit 1
        Bit 0
        Port Pin 7
        Port Pin 6
        Port Pin 5
        Port Pin 4
        Port Pin 3
        Port Pin 2
        Port Pin 1
        Port Pin 0
        Enable Out Registers – Ports A, B, C and F
        Bit definitions: Read Only Registers
        Register Bit <j> = 0 indicates Port pin driver is in tri-state mode (default).
        Register Bit <j> = 1 indicates Port pin driver is enabled.
        相關(guān)PDF資料
        PDF描述
        PSD835F1-12UI Single Ended Active Clamp/Reset PWM 16-SOIC -40 to 85
        PSD835F1-15B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
        PSD835F1-15B81I Single Ended Active Clamp/Reset PWM 16-SOIC -40 to 85
        PSD835F1-15J Single Ended Active Clamp/Reset PWM 16-SOIC -40 to 85
        PSD835F1-15JI Single Ended Active Clamp/Reset PWM 16-PDIP -40 to 85
        相關(guān)代理商/技術(shù)參數(shù)
        參數(shù)描述
        PSD835G2-70U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
        PSD835G2-90U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
        PSD835G2-90UI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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