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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD8144V20MT

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
中文描述：
Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器

    

    
文件頁(yè)數(shù)：
70/110頁(yè)

    

    
文件大?。?/td>
1737K

    

    
代理商：
PSD8144V20MT


    

    

    

	
    
    
    

    
    
	
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    70/110
    JTAG Extensions
    TSTAT and TERR are two JTAG extension signals
    enabled by an “ISC_ENABLE” command received
    over the four standard JTAG signals (TMS, TCK,
    TDI, and TDO). They are used to speed Program
    and Erase cycles by indicating status on PSD sig-
    nals instead of having to scan the status out seri-
    ally using the standard JTAG channel. See
    Application Note 
    AN1153
    .
    TERR indicates if an error has occurred when
    erasing a sector or programming a byte in Flash
    memory. This signal goes Low (active) when an
    Error condition occurs, and stays Low until an
    “ISC_CLEAR” command is executed or a chip Re-
    set (RESET) pulse is received after an
    “ISC_DISABLE” command.
    TSTAT behaves the same as Ready/Busy de-
    scribed in the section entitled 
    Ready/Busy
    (PC3), page 20
    . TSTAT is High when the PSD de-
    vice is in READ Mode (primary and secondary
    Flash memory contents can be read). TSTAT is
    Low when Flash memory Program or Erase cycles
    are in progress, and also when data is being writ-
    ten to the secondary Flash memory.
    TSTAT and TERR can be configured as open-
    drain type signals during an “ISC_ENABLE” com-
    mand. This facilitates a wired-OR connection of
    TSTAT signals from multiple PSD devices and a
    wired-OR connection of TERR signals from those
    same devices. This is useful when several PSD
    devices are “chained” together in a JTAG environ-
    ment.
    Security and Flash memory Protection
    When the security bit is set, the device cannot be
    read on a Device Programmer or through the
    JTAG Port. When using the JTAG Port, only a Full
    Chip Erase command is allowed.
    All other Program, Erase and Verify commands
    are blocked. Full Chip Erase returns the part to a
    non-secured blank state. The Security Bit can be
    set in PSDsoft Express Configuration.
    All primary and secondary Flash memory sectors
    can individually be sector protected against era-
    sures. The sector protect bits can be set in PSD-
    soft Express Configuration.
    Table 34. JTAG Port Signals
    Port C Pin
    JTAG Signals
    Description
    PC0
    TMS
    Mode Select
    PC1
    TCK
    Clock
    PC3
    TSTAT
    Status
    PC4
    TERR
    Error Flag
    PC5
    TDI
    Serial Data In
    PC6
    TDO
    Serial Data Out
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
PSD8144V70MIT
Isolated Feedback Generator 14-SOIC 0 to 70

    

    
PSD8144V70MT
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
PSD8144V90MIT
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
PSD8144V90MT
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
PSD814512JIT
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD833F2-90J
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD833F2-90JI
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

    

    
PSD833F2-90M
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

    

    
PSD833F2-90MI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD834F2-15M
 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP

    

    
    
    
    
	
    	
    
    
     
     
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