- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378074 > PSD813F5 (意法半導(dǎo)體) Flash In-System Programmable ISP Peripherals For 8-bit MCUs PDF資料下載
參數(shù)資料
| 型號： | PSD813F5 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁數(shù)： | 41/110頁 |
| 文件大?。?/td> | 1685K |
| 代理商： | PSD813F5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁
41/110
PSD813F1
Input Macrocells (IMC)
The CPLD has 24 IMCs, one for each pin on Ports
A, B, and C. The architecture of the IMC is shown
in
Figure 19., page 42
. The IMCs are individually
configurable, and can be used as a latch, register,
or to pass incoming Port signals prior to driving
them onto the PLD input bus. The outputs of the
IMCs can be read by the microcontroller through
the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND array or the
MCU address strobe (ALE/AS). Each product term
output is used to latch or clock four IMCs. Port in-
puts 3-0 can be controlled by one product term
and 7-4 by another.
Configurations for the IMCs are specified by equa-
tions written in PSDabel (see Application Note 55).
Outputs of the IMCs can be read by the MCU via
the IMC buffer. See the I/O Port section on how to
read the IMCs.
IMCs can use the address strobe to latch address
bits higher than A15. Any latched addresses are
routed to the PLDs as inputs.
IMCs are particularly useful with handshaking
communication applications where two proces-
sors pass data back and forth through a common
mailbox.
Figure 20., page 43
shows a typical con-
figuration where the Master MCU writes to the Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the
“
Slave-
Read
”
output enable product term.
The Slave can also write to the Port A IMCs and
the Master can then read the IMCs directly.
Note that the
“
Slave-Read
”
and
“
Slave-wr
”
signals
are product terms that are derived from the Slave
MCU inputs RD, WR, and Slave_CS.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD813F2-12J | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F2-12JI | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F2-12JIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F2-12JT | Miniature Switch, High Precision |
| PSD813F2-15UIT | 500 MHz, 45 dB Linear-in-dB Variable Gain Amplifier; Package: TSSOP; No of Pins: 14; Temperature Range: Industrial |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD813F5-12JI | 制造商:WSI 功能描述: |
| PSD813F5-15JI | 制造商:WSI 功能描述: |
| PSD813F5-15U | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
| PSD813F5-90J | 制造商:WSI 功能描述: |
| PSD813F5-90U | 制造商:WSI 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。