參數(shù)資料
型號(hào)： PSD813F4-15J
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 64/103頁
文件大?。?/td> 1180K
代理商： PSD813F4-15J
63/103
PSD8XXF2/3/4/5
RESET TIMING AND DEVICE STATUS AT RESET
Upon Power-up, the PSD8XXFX requires a Reset
(RESET) pulse of duration tNLNH-PO after VCC is
steady. During this period, the device loads inter-
nal configurations, clears some of the registers
and sets the Flash memory into Operating mode.
After the rising edge of Reset (RESET), the
PSD8XXFX remains in the Reset mode for an ad-
ditional period, tOPR, before the first memory ac-
cess is allowed.
The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR, CNTL0) High, during Power On Re-
set for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
Flash memory WRITE cycle initiation is prevented
automatically when VCC is below VLKO.
Warm Reset
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
tNLNH. The same tOPR period is needed before the
device is operational after warm reset. Figure 31
shows the timing of the Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset
Table 33 shows the I/O pin, register and PLD sta-
tus during Power On Reset, warm reset and Pow-
er-down mode. PLD outputs are always valid
during warm reset, and they are valid in Power On
Reset once the internal PSD8XXFX Configuration
bits are loaded. This loading of PSD8XXFX is
completed typically long before the VCC ramps up
to operating level. Once the PLD is active, the
state of the outputs are determined by the PSDa-
bel equations.
Reset of Flash Memory Erase and Program
Cycles (on the PSD834Fx)
A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET) termi-
nates the cycle and returns the Flash memory to
the Read Mode within a period of tNLNH-A.
Figure 31. Reset (RESET) Timing
tNLNH-PO
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
tOPR
VCC
V
CC(min)
Power-On Reset
Warm Reset
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813F4-15JI 制造商:WSI 功能描述:
PSD813F4A-90J 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD813F2A-90J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD813F4A-90M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD813F2A-90M RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD813F4VA-15J 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD813F2VA-15J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD813F4VA-15U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD813F2VA-15U RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
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