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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD813370JIT

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
中文描述：
Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器

    

    
文件頁(yè)數(shù)：
65/110頁(yè)

    

    
文件大?。?/td>
1737K

    

    
代理商：
PSD813370JIT


    

    

    

	
    
    
    

    
    
	
    65/110
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    Table 30. Power Management Mode Registers PMMR0 (Note 1)
    Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
    Table 31. Power Management Mode Registers PMMR2 (Note 1)
    Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
    Bit 0
    X
    0
    Not used, and should be set to zero.
    Bit 1
    APD Enable
    0 = off Automatic Power-down (APD) is disabled.
    1 = on Automatic Power-down (APD) is enabled.
    Bit 2
    X
    0
    Not used, and should be set to zero.
    Bit 3
    PLD Turbo
    0 = on PLD Turbo mode is on
    1 = off PLD Turbo mode is off, saving power.
    Bit 4
    PLD Array clk
    0 = on
    CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN 
    (PD1) Powers-up the PLD when Turbo Bit is ’0.’
    1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
    Bit 5
    PLD MCell clk
    0 = on CLKIN (PD1) input to the PLD macrocells is connected.
    1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
    Bit 6
    X
    0
    Not used, and should be set to zero.
    Bit 7
    X
    0
    Not used, and should be set to zero.
    Bit 0
    X
    0
    Not used, and should be set to zero.
    Bit 1
    X
    0
    Not used, and should be set to zero.
    Bit 2
    PLD Array 
    CNTL0
    0 = on Cntl0 input to the PLD AND Array is connected.
    1 = off Cntl0 input to PLD AND Array is disconnected, saving power.
    Bit 3
    PLD Array 
    CNTL1
    0 = on Cntl1 input to the PLD AND Array is connected.
    1 = off Cntl1 input to PLD AND Array is disconnected, saving power.
    Bit 4
    PLD Array 
    CNTL2
    0 = on Cntl2 input to the PLD AND Array is connected.
    1 = off Cntl2 input to PLD AND Array is disconnected, saving power.
    Bit 5
    PLD Array 
    ALE
    0 = on ALE input to the PLD AND Array is connected.
    1 = off ALE input to PLD AND Array is disconnected, saving power.
    Bit 6
    PLD Array 
    DBE
    0 = on DBE input to the PLD AND Array is connected.
    1 = off DBE input to PLD AND Array is disconnected, saving power.
    Bit 7
    X
    0
    Not used, and should be set to zero.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
PSD813390JIT
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
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Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD813370JT
 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
PSD813370MIT
 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
PSD813370MT
 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
PSD813390JIT
 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
PSD813390JT
 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
    
    
    
	
    	
    
    
     
     
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