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| 型號(hào)： | PSD712S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個(gè)可編程輸入/輸出，通用PLD的有66個(gè)輸入） |
| 文件頁數(shù)： | 60/104頁 |
| 文件大?。?/td> | 515K |
| 代理商： | PSD712S5 |
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PSD7XX Family
13-60
The PSD7XX offers a number of configurable power saving options which include the
Automatic Power Down (APD) Logic and the Power Management Mode Registers (PMMR0
and PMMR1). The APD Logic allows the PSD7XX to enter into either Power Down or
Sleep Mode automatically, while the PMMRs can be configured at run time by the
microcontroller to selectively reduce the power consumption of the PSD functional blocks.
The APD Logic and Power Down Mode
The Automatic Power Down (APD) logic puts the PSD7XX into power savings mode by
monitoring the activity of the address strobe (ALE/AS). If the APD unit is enabled, the
four-bit APD counter starts counting whenever the address strobe is inactive. If the strobe
remains inactive for fifteen CLKIN clock periods, the power down (PDN) signal will become
active and the PSD7XX enter into either Power Down or Sleep Mode. Immediately after
ALE starts pulsing the PSD7XX will return to normal operation. The APD counter clock
source comes from the CLKIN pin which is pin PD1 on Port D or the Superv_Clk from the
Supervisory Function. In order to guarantee that the APD counter will not overflow when
enabled, there should be less than 15 clocks between two successive ALE pulses.
Usually, microcontrollers entering power down mode will freeze their ALE at logic high or
low level. By programming bit 0 of PMMR0, the APD knows when the MCU is in power
down mode. If the APD detects the ALE level is in the power down state for 15 CLKIN
periods, then the PSD7XX will enter a power down mode. To enable the APD operation, the
APD bit in the PMMR0 should be set to “1”.
When the address strobe starts pulsing again, or the CSI input switches from high to low,
the PSD7XX will return to normal activity.
When the PDN signal is set to “1” (active state) in Power Down (or Sleep Mode), the
PSD7XX MCU bus interface is disabled and all MCU inputs (address, data and control
signals) are blocked from entering the device. If the clock input to the PLD is not needed
in Power Down mode, it should be blocked to save power by setting Bit 4 and 5 in the
PMMR0 to “1”.
Sleep Mode
The Sleep Mode is activated if the Sleep mode bit, the APD bit and the ALE Polarity bit in
the PMMRs are set, and the APD Counter has overflowed after 15 CLKIN clocks
(see Figure 29). In Sleep Mode the PSD7XX consumes less power than the Power Down
Mode, with typical I
CC
reduced to 25μA.
In this mode, the PLD still monitors the inputs and responds to them. As soon as the ALE
starts pulsing or the CSI input switches from high to low, the PSD7XX exits the Sleep Mode.
The PSD7XX access time from Sleep Mode is specified by tLVDV1. The PLD response time
to an input transition is specified by tLVDV2.
Power
Management
Unit
Port Function
Pin Level
MCU I/O
PLD Out
Address Out
Data Port
Peripheral I/O
No Change
No Change
Undefined
Three-State
Three-State
Table 31. Power Down Effect on Ports
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