參數(shù)資料
型號(hào)： PSD502B1
英文描述： 60V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-254AA package; Similar to IRHMB57064 with optional Total Dose Rating of 1000kRads
中文描述： PSD5XX/ZPSD5XX家庭領(lǐng)域，可編程微控制器外設(shè)
文件頁數(shù)： 4/153頁
文件大小： 1036K
代理商： PSD502B1
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Introduction
Programmable Peripheral
PSD5XX Famly
Field-Programmable Microcontroller Peripherals
The PSD5XX family is a microcontroller peripheral that integrates high-performance and
user-configurable blocks of EPROM, programmable logic, and SRAM into one part. The
PSD5XX is also loaded with a variety of features, such as Counter/Timers, Interrupt
controller, power management, and page logic. The PSD5XX products also provide a
powerful microcontroller interface that eliminates the need for external “glue logic”. The no
“glue logic” concept provides a user-programmable interface to a variety of 8- and 16-bit
(multiplexed or non-multiplexed) microcontrollers that is easy to use. The part’s integration,
small form factor, low power consumption, and ease of use make it the ideal part for
interfacing to virtually any microcontroller.
The PSD5XX provides three Zero-power PLDs (ZPLDs): a Decode PLD (DPLD), a
General-purpose PLD (PLD), and a Peripheral PLD (PPLD). The ZPLDs have a total of 61
inputs, 140 product terms, 30 macrocells, and 24 I/O connections. A configuration bit
(Turbo) can be set by the MCU, and will automatically place the ZPLDs into standby if
no inputs are changing. The ZPLDs are designed to consume minimum power using Zero
Power CMOS technology that uses low standby current. Unused product terms are
automatically disabled, also reducing power, regardless of the Turbo bit setting.
The main function of the DPLD is to perform address decoding for the internal I/O ports,
EPROM, and SRAM. The address decoding can be based on up to 24 bits of address
inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports
separate program and data spaces (for 8031 compatible MCUs).
The General-purpose PLD (GPLD) can be used to implement various logic defined by the
user, such as:
State machines
Loadable counters and shift registers
Inter-processor mailbox
External control logic (chip selects, output enables, etc.).
The GPLD has access to up to 61 inputs, 118 product terms, 24 macrocells, and 24 I/O
pins.
相關(guān)PDF資料
PDF描述
PSD511B1 PSD5XX/ZPSD5XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS
PSD512B0 500V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-205AF package; A IRHF7430SE with Standard Packaging
PSD512B1 -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA597160 with optional Total Dose Rating of 300kRads
PSD511B1-C-70U Low Cost Field Programmable Microcontroller Peripherals
PSD501B1-C-90JI Low Cost Field Programmable Microcontroller Peripherals
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD502B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD502B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD502B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD502B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD502B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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