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參數資料
| 型號： | PSD4XX |
| 廠商： | 意法半導體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現(xiàn)場可編程微控制器外圍設備 |
| 文件頁數： | 9/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD4XX |
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PSD4XX Famly
6
Figure 3. PSDsoft Development Tools
PSDsilos III
SILOSIII
CHIP SIMULATION
PSD Programmer
PSDpro/MagicPro
CHIP PROGRAMMING
PSD Compiler
(ZPLD FITTING, ADDRESS TRANSLATION)
PSDabel
ZPLD DESCRIPTION
(STATE MACHINE, DECODING)
PSDsoft
Development Software
PSD Configuration
CHIP CONFIGURATION
THIRD PARTY
PROGRAMMERS
CODE FILE
Shown in Figure 3 (below) is the software design flow for a PSD4XX device.
PSDsoft—
ST
’s software development suite—is used throughout the design phase. You
start with a design file that is written in PSDabel—a high-level hardware description
language (HDL). Before you compile your design, you must also configure the PSD4XX so
it knows what signals to expect from your microprocessor and what pre-runtime options
should be set (such as the security bit).
Once you have a design file and have configured the device, you are ready to run the Fitter
and Address Translator. The Fitter accepts input from PSDabel and PSD Configuration,
synthesizes this user logic and configuration, and fits the design to the PSD silicon. The
Address Translator process allows the user to map the MCU firmware from a cross-
compiler (in Intel HEX or S-Record format) into the NVM memory blocks within the PSD. As
a result, the MCU firmware is merged with the logic and configuration definition of the PSD.
The output of the Address Translator and the Fitter is the required object file that is used by
a programmer to program the PSD device. The object file includes chip configuration, the
PLD fusemap, and MCU firmware information.
PSDsilosIII is an optional program that provides functional chip-level simulation of the
PSD4XX. PSDsoft automatically creates files for input to the simulator. These files convey
relevant design information to the simulator. As a result, the user only has to create a
stimulus file since all of the signals and node names are taken from the design file.
6.0
Design Flow
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