參數(shù)資料
型號: PSD4235G2V-12M
廠商: 意法半導(dǎo)體
英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁數(shù): 78/93頁
文件大小: 503K
代理商: PSD4235G2V-12M
Preliminary Information
PSD4000 Series
75
-90
-12
Turbo
Off
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
t
AVQV
t
SLQV
ALE or AS Pulse Width
22
24
ns
Address Setup Time
(Note 3)
7
9
ns
Address Hold Time
(Note 3)
8
10
ns
Address Valid to Data Valid
(Note 3)
90
120
Add 20**
ns
CS Valid to Data Valid
90
120
ns
RD to Data Valid
(Note 5)
35
35
ns
t
RLQV
RD or PSEN to Data Valid,
80C51XA Mode
(Note 2)
45
48
ns
t
RHQX
t
RLRH
t
RHQZ
t
EHEL
t
THEH
t
ELTL
RD Data Hold Time
(Note 1)
0
0
ns
RD Pulse Width
(Note 1)
36
40
ns
RD to Data High-Z
(Note 1)
38
40
ns
E Pulse Width
38
42
ns
R/W Setup Time to Enable
10
16
ns
R/W Hold Time After Enable
0
0
ns
t
AVPV
Address Input Valid to
Address Output Delay
(Note 4)
30
35
ns
Read Timing
(3.0 V to 3.6 V Versions)
Microcontroller Interface – PSD4000 AC/DC Parameters
(3.0 V to 3.6 V Versions)
NOTES:
1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 80C51XA.
3. Any input used to select an internal PSD4135G2V function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
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PSD4235F1-12U High Speed CMOS Logic 3-to-8 Line Decoder/Demultiplexer with Address Latches 16-SOIC -55 to 125
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