參數(shù)資料
型號： PSD4235G2
英文描述： FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY)
中文描述： Flash在系統(tǒng)編程（ISP）外設(shè)的16位微控制器（5V電源）
文件頁數(shù)： 63/89頁
文件大小： 703K
代理商： PSD4235G2
63/89
PSD4235G2
Figure 34. Reset (RESET) Timing
Programming In-Circuit using the JTAG Serial
Interface
The JTAG Serial Interface on the PSD can be en-
abled on Port E (see Table 52). All memory blocks
(primary Flash memory and secondary Flash
memory), PLD logic, and PSD Configuration bits
may be programmed through the JTAG-ISC Serial
Interface. A blank device can be mounted on a
printed circuit board and programmed using JTAG
In-System Programming (ISP).
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.
By default, on a blank PSD (as shipped from the
factory, or after erasure), four pins on Port E are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO.
See Application Note AN1153 for more details on
JTAG In-System Programming (ISP).
Standard JTAG Signals.
The standard JTAG
signals (TMS, TCK, TDI, and TDO) can be en-
abled by any of three different conditions that are
logically ORed. When enabled, TDI, TDO, TCK,
and TMS are inputs, waiting for a serial command
from an external JTAG controller device (such as
FlashLINK or Automated Test Equipment). When
the enabling command is received from the exter-
nal JTAG controller device, TDO becomes an out-
put and the JTAG channel is fully functional inside
the PSD. The same command that enables the
JTAG channel may optionally enable the two addi-
tional JTAG pins, TSTAT and TERR.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG pins
(TMS, TCK, TDI, and TDO) on their respective
Port E pins. For purposes of discussion, the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD I/O.
JTAG_ON = PSDsoft Express_enabled +
/* An NVM configuration bit inside the
PSD is set by the designer in the
PSDsoft Express Configuration utility.
This dedicates the pins for JTAG at all
times (compliant with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a bit at
run-time
by
writing
register, JTAG Enable. This register
is located at address CSIOP + offset
C7h. Setting the JTAG_ENABLE bit in
this register will enable the pins for
JTAG use. This bit is cleared by a PSD
reset or the microcontroller. See
Table 21 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside
the PSD can be used to enable the JTAG
pins. This PT has the reserved name
JTAGSEL. Once defined as a node in
PSDabel, the designer can write an
equation for JTAGSEL. This method is
used when the Port E JTAG pins are
multiplexed with other I/O signals. It
is recommended to tie logically the
node JTAGSEL to the JEN\ signal on the
Flashlink cable when multiplexing JTAG
signals. See Application Note 1153 for
details. */
The state of the PSD Reset (RESET) signal does
not interrupt (or prevent) JTAG operations if the
JTAG pins are dedicated by an NVM configuration
bit (via PSDsoft Express). However, Reset (RE-
SET) will prevent or interrupt JTAG operations if
the JTAG Enable Register (as shown in Table 21)
is used to enable the JTAG pins.
The PSD supports JTAG In-System-Programma-
bility (ISP) commands, but not Boundary Scan.
ST’s PSDsoft Express software tool and
FlashLINK JTAG programming cable implement
the JTAG In-System-Programmability (ISP) com-
mands.
to
the
PSD
Table 52. JTAG Port Signals
tNLNH-PO
Power-On Reset
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
Warm Reset
tOPR
V
CC
V
CC
(min)
Port E Pin
JTAG Signals
Description
PE0
TMS
Mode Select
PE1
TCK
Clock
PE2
TDI
Serial Data In
PE3
TDO
Serial Data Out
相關(guān)PDF資料
PDF描述
PSD4235G2V -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging
PSD4235G1-B-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235F2-A-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235G2-A-12J Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235G1-12B81 Flash In-System-Programmable Peripherals for 16-Bit MCUs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD4235G2-70U 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2-90UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-12UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*