參數(shù)資料
型號(hào)： PSD4235G2-B-90UI
廠商： 意法半導(dǎo)體
英文描述： CAP 4.7UF 4V 10% TANT SMD-3216-18 TR-7-PL SN/PB5%
中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁(yè)數(shù)： 51/93頁(yè)
文件大?。?/td> 503K
代理商： PSD4235G2-B-90UI
PSD4000 Series
Preliminary Information
48
Control
Register
Setting
Direction
Register
Setting
VM
Defined In
PSDsoft
Register
Setting
Mode
Declare
pins only
0
1= output,
0= input
MCU I/O
(Note 1)
NA
Declare pins
and logic or chip
select equations
PLD I/O
NA
NA
Data Port
(Port F, G)
Selected for
MCU with
non-mux bus
NA
NA
NA
Address Out
(Port E, F, G)
Declare
pins only
1
1
NA
Address In
(Port A,B,C,D,F)
Declare pins
NA
NA
NA
JTAG ISP
Declare pins
only
NA
NA
NA
MCU Reset
Mode
Specify pin
logic level
NA
NA
NA
Table 17. Port Operating Mode Settings
*
NA = Not Applicable
NOTE:
1. Control Register setting is not applicable to Ports A, B and C.
9.4.2.1 MCU I/OMode
In the MCU I/O Mode, the microcontroller uses the PSD4000 ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD4000 are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 6.
A port pin can be put into MCU I/O mode by writing a
‘
0
’
to the corresponding bit in the
Control Register (Port E, F and G). The MCU I/O direction may be changed by writing
to the corresponding bit in the Direction Register. See the subsection on the Direction
Register in the
“
Port Registers
”
section. When the pin is configured as an output, the
content of the Data Out Register drives the pin. When configured as an input, the
microcontroller can read the port input through the Data In buffer. See Figure 20.
Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default.
They can be used for PLD I/O if they are specified in PSDsoft.
9.4.2.2 PLD I/OMode
The PLD I/O Mode uses a port as an input to the CPLD
’
s Input Micro
Cells, and/or
as an output from the GPLD. The corresponding bit in the Direction Register must not be
set to
‘
1
’
if the pin is defined as a PLD input pin in PSDsoft. The PLD I/O Mode is specified
in PSDsoft by declaring the port pins, and then specifying an equation in PSDsoft.
The
PSD4000
Functional
Blocks
(cont.)
相關(guān)PDF資料
PDF描述
PSD4235G2-C-12JI CAP 4.7UF 4V 10% TANT SMD-3216-18 TR-7-PL SN100%
PSD4235G2-C-12M Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2-C-12MI Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2-C-12U CAP 4.7UF 6.3V 10% TANT SMD-3216-18 TR-13-PL GOLD
PSD4235G2-C-12UI CAP 4.7UF 6.3V 10% TANT SMD-3216-18 TR-13-PL SN/PB5%
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