參數(shù)資料
型號： PSD4235G2-B-20U
廠商： 意法半導(dǎo)體
英文描述： CAP 0.47UF 25V 10% TANT SMD-3216-18 TR-13-PL SN100%
中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁數(shù)： 59/93頁
文件大?。?/td> 503K
代理商： PSD4235G2-B-20U
PSD4000 Series
Preliminary Information
56
The
PSD4000
Functional
Blocks
(cont.)
Access
5V V
CC
,
Typical
Standby
Current
50 μA
(Note 2)
PLD
Memory
Access
Time
Recovery Time
to Normal
Access
Propagation
Delay
Normal tpd
(Note 1)
Mode
Power Down
No Access
tLVDV
Table 25. PSD4000 Timing and Standby Current During Power
Down Mode
NOTES:
1. Power Down does not affect the operation of the PLD. The PLD operation in this
mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and
the PLD Turbo bit is off.
Port Function
MCU I/O
PLD Out
Address Out
Data Port
Peripheral I/O
Pin Level
No Change
No Change
Undefined
Three-State
Three-State
Table 24. Power Down Mode’s Effect on
Ports
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.)
Power Down Mode
By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled.
The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive
for fifteen CLKIN (pin PD1) clock periods.
The following should be kept in mind when the PSD is in Power Down Mode:
If the address strobe starts pulsing again, the PSD will return to normal operation.
The PSD will also return to normal operation if either the CSI input returns low or the
Reset input returns high.
The MCU address/data bus is blocked from all memories and PLDs.
Various signals can be blocked (prior to Power Down Mode) from entering the PLDs
by setting the appropriate bits in the PMMR registers. The blocked signals include
MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from
the PLDs will not block CLKIN from the APD unit.
All PSD memories enter Standby Mode and are drawing standby current. However,
the PLDs and I/O ports do
not
go into Standby Mode because you don
’
t want to
have to wait for the logic and I/O to
“
wake-up
”
before their outputs can change. See
Table 24 for Power Down Mode effects on PSD ports.
Typical standby current is 50 μA for 5 V parts. This standby current value assumes
that there are no transitions on any PLD input.
相關(guān)PDF資料
PDF描述
PSD4235G2-B-20UI CAP 0.47UF 25V 10% TANT SMD-3216-18 TR-13-PL SN100%
PSD4235G2-B-90U Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2-B-90UI CAP 4.7UF 4V 10% TANT SMD-3216-18 TR-7-PL SN/PB5%
PSD4235G2-C-12JI CAP 4.7UF 4V 10% TANT SMD-3216-18 TR-7-PL SN100%
PSD4235G2-C-12M Flash In-System-Programmable Peripherals for 16-Bit MCUs
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