參數(shù)資料
        

        


        


        
型號(hào)：
PSD4235G1V-A-12M

        

        
廠商：
意法半導(dǎo)體

        

        
英文描述：
Flash In-System-Programmable Peripherals for 16-Bit MCUs

        

        
中文描述：
Flash在系統(tǒng)可編程外設(shè)的16位微控制器

        

        
文件頁(yè)數(shù)：
53/93頁(yè)

        

        
文件大小：
503K

        

        
代理商：
PSD4235G1V-A-12M


        

        

        

	
        
    
    

    
        
	
        PSD4000 Series
        Preliminary Information
        50
        9.4.3   Port Configuration Registers (PCRs)
        Each port has a set of PCRs used for configuration. The contents of the registers can be 
        accessed by the microcontroller through normal read/write bus cycles at the addresses
        given in Table 6. The addresses in Table 6 are the offsets in hex from the base of the
        CSIOP register.
        The pins of a port are individually configurable and each bit in the register controls its
        respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,
        shown in Table 19, are used for setting the port configurations. The default power-up state
        for each register in Table 22 is 00h.
        Register Name
        Port
        MCU Access
        Control
        Direction
        Drive Select*
        E,F,G
        A,B,C,D,E,F,G
        A,B,C,D,E,F,G
        Write/Read
        Write/Read
        Write/Read
        Table 19.  Port Configuration Registers
        *
        NOTE:
         See Table 22 for Drive Register bit definition.
        The 
        PSD4000
        Functional
        Blocks
        (cont.)
        9.4.3.1   Control Register
        Any bit set to 
        ‘
        0
        ’
         in the Control Register sets the corresponding Port pin to MCU I/O Mode, 
        and a 
        ‘
        1
        ’
         sets it to Address Out Mode. The default mode is MCU I/O. Only Ports E, F and
        G have an associated Control Register.
        9.4.3.2   Direction Register
        The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to 
        ‘
        1
        ’
        in the Direction Register will cause the corresponding pin to be an output, and any bit set
        to 
        ‘
        0
        ’
         will cause it to be an input. The default mode for all port pins is input.
        Figures 21 and 23 show the Port Architecture diagrams for Ports A/B/C and E/F/G 
        respectively. The direction of data flow for Ports A, B, C and F are controlled by the 
        direction register.
        An example of a configuration for a port with the three least significant bits set to output
        and the remainder set to input is shown in Table 21. Since Port D only contains four pins,
        the Direction Register for Port D has only the four least significant bits active.
        Direction Register Bit
        0
        1
        Port Pin Mode
        Input
        Output
        Table 20. Port Pin Direction Control 
        Bit 7
        Bit 6
        Bit 5
        Bit 4
        Bit 3
        Bit 2
        Bit 1
        Bit 0
        0
        0
        0
        0
        0
        1
        1
        1
        Table 21.  Port Direction Assignment Example
        
    
        
    
    
        


        


        

        相關(guān)PDF資料
        		

        PDF描述
        		

        
        

        
PSD4235G1V-A-12MI
Flash In-System-Programmable Peripherals for 16-Bit MCUs

        

        
PSD4235G1V-A-12U
Flash In-System-Programmable Peripherals for 16-Bit MCUs

        

        
PSD4235G1V-A-12UI
Flash In-System-Programmable Peripherals for 16-Bit MCUs

        

        
PSD4235G1V-A-15B81
Flash In-System-Programmable Peripherals for 16-Bit MCUs

        

        
PSD4235G1V-A-15B81I
CAP TANT 100UF 20V 20% SMD

        

        

        

        


        


        

        相關(guān)代理商/技術(shù)參數(shù)
        		

        參數(shù)描述
        		

        
        

        
PSD4235G2-70U
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

        

        
PSD4235G2-90U
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

        

        
PSD4235G2-90UI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

        

        
PSD4235G2V-12UI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

        

        
PSD4235G2V-90U
功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

        

        
    
    
    
	
        	
    
    
     
     
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