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參數(shù)資料
| 型號： | PSD4235F3V-A-70JI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁數(shù)： | 52/93頁 |
| 文件大?。?/td> | 503K |
| 代理商： | PSD4235F3V-A-70JI |
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Preliminary Information
PSD4000 Series
49
The
PSD4000
Functional
Blocks
(cont.)
9.4.2.4 Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Ports A, B, C, D or F and are routed as inputs to the PLDs. The address
input can be latched by the address strobe (ALE/AS). Any input that is included in the
DPLD equations for the Main Flash, Boot Flash, or SRAM is considered to be an address
input.
9.4.2.5 Data Port Mode
Port F and G can be used as a data bus port for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port F and G if the ports are configured as Data Port.
Data Port Mode is automatically configured in PSDsoft when a non-multiplexed bus MCU
is selected.
9.4.2.6 JTAG ISP
Port E is JTAG compliant, and can be used for In-System Programming (ISP).
9.4.2.7 MCU Reset Mode
Port F and G can be configured to operate in
“
MCU Reset
”
mode. This mode is available
when PSD is configured for the Motorola 16-bit 683XX and HC16 family and is active only
during reset.
At the rising edge of the Reset input, the MCU reads the logic level on the Data Bus D15-0
pins. The MCU then configures some of its I/O pin functions according to the logic level
input on the data bus lines. Two dedicated buffers are usually enabled during reset to drive
the data bus lines to the desired logic level.
The PSD4135G2 can replace the two buffers by configuring Port F and G to operate in
MCU Reset Mode. In this mode, the PSD will drive the pre-defined logic level or data
pattern onto the MCU Data Bus when reset is active and there is no ongoing bus cycle.
After reset, Port F and G return to the normal Data Port Mode.
The MCU Reset Mode is enabled and configured in PSDsoft. The user defines the logic
level (data pattern) that will be driven out from Port F and G during reset.
9.4.2.3 Address Out Mode
For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used
to drive latched addresses onto the port pins. These port pins can, in turn, drive external
devices. Either the output enable or the corresponding bits of both the Direction Register
and Control Register must be set to a
‘
1
’
for pins to use Address Out Mode. This must be
done by the MCU at run-time. See Table 18 for the address output pin assignments on
Ports E, F and F for various MCUs.
Note:
Do not drive address lines with Address Out Mode to an external memory device if
it is intended for the MCU to boot from the external device. The MCU must first boot from
PSD memory so the Direction and Control register bits can be set.
MCU
Port E (3:0)
Port E (7:4)
Port F (3:0)
Port F (7:4)
Port G (3:0)
Port G (7:4)
80C51XA
N/A
Addr (7:4)
N/A
Addr (7:4)
Addr (11:8)
Addr (15:12)
All Other
MCU with
Multiplexed
Bus
Addr (3:0)
Addr (7:4)
Addr (3:0)
Addr (7:4)
Addr (11:8)
Addr (15:12)
Table 18. I/OPort Latched Address Output Assignments
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4235F3V-A-70M | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F3V-A-90U | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F3V-A-90UI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F3V-B-12B81I | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F3V-B-12J | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-12UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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