參數(shù)資料
型號: PSD413A1-C-15J
廠商: 意法半導(dǎo)體
英文描述: BBG ECL OR DUAL 3INPUT; Package: 20 LEAD PLLC; No of Pins: 20; Container: Tape and Reel; Qty per Container: 500
中文描述: 低成本現(xiàn)場可編程微控制器外圍設(shè)備
文件頁數(shù): 57/123頁
文件大?。?/td> 657K
代理商: PSD413A1-C-15J
PSD4XX Famly
54
9.3.10 Port A – Functionality and Structure
Port A is the most flexible of all the I/O ports. It can be configured to perform one or more
of the following functions:
J
Standard MCU I/O Mode
J
PLD I/O
J
Address Out – latched address lines A[0-7] are assigned to pins PA[0-7].
J
Address In – input port for other address lines, inputs can be latched by ALE.
J
Peripheral I/O
Figure 27 shows the structure of a Port A pin. If the pin is configured as an output port,
the multiplexer selects one of its three inputs as output. If the pin is configured as an input,
the input connects to :
1. Data In Register as input in Standard MCU I/O Mode
or
2. PA Macrocell as PLD input
or
3. PA Macrocell through a latch latched by ALE, as Address In input.
9.3.11 Port B – Functionality and Structure
Port B is similar to Port A in structure. It can be configured to perform one or more of the
following functions:
J
Standard MCU I/O Mode
J
PLD I/O
J
Address Out – address lines A[0-7] for 8-bit multiplexed bus or address lines
A[8-15] for 16-bit multiplexed bus are assigned to pins PB[0-7].
Figure 28 shows the structure of a Port B pin. If the pin is configured as an output port,
the multiplexer selects one of its three inputs as output. If the pin is configured as input,
the input connects to :
J
Data In Register as input in Standard MCU I/O Mode
or
J
PB Macrocell as PLD input
The PSD4XX
Architecture
(cont.)
相關(guān)PDF資料
PDF描述
PSD413A1-C-15L 3-Input 3-Output OR Gate; Package: SOEIAJ-16; No of Pins: 16; Container: Rail; Qty per Container: 50
PSD401A1-C-12J HDC-HD-15BCM RoHS Compliant: Yes
PSD401A1-C-15J Low Cost Field Programmable Microcontroller Peripherals
PSD401A1-C-15L Low Cost Field Programmable Microcontroller Peripherals
PSD401A1-C-15U CONN MALE INSERT HA SIZE 5 16POS
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