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| 型號(hào)： | PSD413A1-12LI |
| 英文描述： | 250V 300kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-0.5 package. Also available with Total Dose Rating of 300kRads.; A IRHNJ67234 with Standard Packaging |
| 中文描述： | 現(xiàn)場(chǎng)可編程外圍 |
| 文件頁(yè)數(shù)： | 74/123頁(yè) |
| 文件大?。?/td> | 657K |
| 代理商： | PSD413A1-12LI |
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PSD4XX Famly
71
The PSD4XX
Architecture
(cont.)
Port Configuration
Pin Status
I/O Port
Unchanged
ZPLD Output
Depend on Inputs to the ZPLD
Address Out
Undefined
Data Port
Tri-stated
Peripheral I/O
Tri-stated
Table 20. I/OPin Status During Power Down And Sleep Mode
J
Input Clock
The PSD4XX provides the option to turn off the clock inputs to save AC power
consumption. The clock input (CLKIN) is used as a source for driving the following
modules:
J
ZPLD Array Clock Input
J
ZPLD MacroCell Clock Flip Flop
J
APD Counter Clock
During power down or if any of the modules are not being used the clock to these
modules should be disabled. To reduce AC power consumption, it is especially
important to disable the clock input to the ZPLD array if it is not used as part of a logic
equation.
The ZPLD Array Clock can be disabled by setting PMMR0 bit 5 (ZPLD ACLK).
The ZPLD MacroCell Clock Input can be disabled by setting PMMR0 bit 6
(ZPLD RCLK). The Timer Clock can be disabled by setting PMMR0 bit 7
(TMR CLK). The APD Counter Clock will be disabled automatically if Power Down or
Sleep Mode is entered through the APD unit. The input buffer of the CLKIN input will be
disabled if bits 5 – 7 PMMR0 are set and the APD has overflowed.
PLD
PLD
Access
Time
Access
Recovery
Time To
Normal
Access
Propagation
Delay
Recovery
Time To
Normal
Operation
Power Down
Normal t
PD
(Note 1)
0
No Access
t
LVDV
Sleep
t
LVDV2
(Note 2)
t
LVDV3
(Note 3)
No Access
t
LVDV1
Summary of PSD4XX Timng and Standby Current During Power Down
and Sleep Modes
NOTES: 1. Power Down does not affect the operation of the ZPLD. The ZPLD operation in this mode is based
only on the ZPLD_Turbo Bit.
2. In Sleep Mode any input to the ZPLD will have a propagation delay of t
LVDV2
.
3. PLD recovery time to normal operation after exiting Sleep Mode. An input to the ZPLD during the
transition will have a propagation delay time of t
LVDV3
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD413A1-12U | -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-1 package; A IRHN9130 with Standard Packaging |
| PSD413A1-12UI | Field-Programmable Peripheral |
| PSD413A2-70U | Field-Programmable Peripheral |
| PSD413A2-90J | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-3 package; A IRHNB7260 with Standard Packaging |
| PSD413A2-90U | 400V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA7360SE with Standard Packaging |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD413A2-C-70L | 制造商:WSI 功能描述: |
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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