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參數(shù)資料
| 型號： | PSD4135G2-C-12UI |
| 廠商： | 意法半導體 |
| 英文描述： | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 4700pF; Working Voltage (Vdc)[max]: 200V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 2225; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.220" x 0.248"; Container: Bulk; Features: Unmarked |
| 中文描述： | Flash在系統(tǒng)可編程外設的16位微控制器 |
| 文件頁數(shù)： | 72/93頁 |
| 文件大小： | 503K |
| 代理商： | PSD4135G2-C-12UI |
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Preliminary Information
PSD4000 Series
69
NOTES:
1.
RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
RD and PSEN have the same timing.
Any input used to select an internal PSD4000 function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
RD timing has the same timing as DS, LDS, and UDS signals.
2.
3.
4.
5.
-70
-90
Turbo
Off
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
t
AVQV
t
SLQV
ALE or AS Pulse Width
15
20
ns
Address Setup Time
(Note 3)
4
6
ns
Address Hold Time
(Note 3)
7
8
ns
Address Valid to Data Valid
(Note 3)
70
90
Add 12**
ns
CS Valid to Data Valid
75
100
ns
RD to Data Valid
(Note 5)
24
32
ns
t
RLQV
RD or PSEN to Data Valid,
80C51XA Mode
(Note 2)
31
38
ns
t
RHQX
t
RLRH
t
RHQZ
t
EHEL
t
THEH
t
ELTL
RD Data Hold Time
(Note 1)
0
0
ns
RD Pulse Width
(Note 1)
27
32
ns
RD to Data High-Z
(Note 1)
20
25
ns
E Pulse Width
27
32
ns
R/W Setup Time to Enable
6
10
ns
R/W Hold Time After Enable
0
0
ns
t
AVPV
Address Input Valid to Address
Output Delay
(Note 4)
20
25
ns
Read Timing
(5 V ± 10% Versions)
Microcontroller Interface – PSD4000 AC/DC Parameters
(5V ±10% Versions)
相關PDF資料 |
PDF描述 |
|---|---|
| PSD4135G2-C-15B81 | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-C-15B81I | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-C-15J | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 8200pF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 2225; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.220" x 0.248"; Container: Bulk; Features: Unmarked |
| PSD4135G2-C-15JI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-C-15M | 18PF/50V 0805 C0G 10% CERAMIC CAPACITOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4135G2-C-15B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-C-15B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-C-15J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-C-15JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-C-15M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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