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    參數(shù)資料
    型號(hào): PSD4135G2-A-70MI
    廠商: 意法半導(dǎo)體
    英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs
    中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器
    文件頁(yè)數(shù): 56/93頁(yè)
    文件大小: 503K
    代理商: PSD4135G2-A-70MI
    Preliminary Information
    PSD4000 Series
    53
    The
    PSD4000
    Functional
    Blocks
    (cont.)
    9.4.6 Port D – Functionality and Structure
    Port D has four I/O pins. See Figure 22. Port D can be configured to program one or more
    of the following functions:
    J
    MCU I/O Mode
    J
    PLD Input
    direct input to PLD
    Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
    J
    PD0
    ALE, as address strobe input
    J
    PD1
    CLKIN, as clock input to the PLD and APD counter
    J
    PD2
    CSI, as active low chip select input. A high input will disable the
    Flash/SRAM and CSIOP.
    J
    PD3
    WRH, as active low Write Enable (high byte) input or as DBE input from
    68HC912
    9.4.7 Port E – Functionality and Structure
    Port E can be configured to perform one or more of the following functions (see Figure 23):
    J
    MCU I/O Mode
    J
    In-System Programming
    JTAG port can be enabled for programming/erase of the
    PSD4000 device. (See Section 9.6 for more information on JTAG programming.)
    Pins that are configured as JTAG pins in PSDsoft will not be available for other I/O
    functions.
    J
    Open Drain
    Port E pins can be configured in Open Drain Mode
    J
    Battery Backup features
    PE6 can be configured as a Battery Input (Vstby) pin.
    PE7 can be configured as a Battery On Indicator output
    pin, indicating when Vcc is less than Vbat.
    J
    Latched Address Output
    Provided latched address (A7-0) output
    I
    DATA OUT
    REG.
    D
    Q
    D
    Q
    WR
    WR
    READ MUX
    P
    D
    B
    PLD INPUT
    DIR REG.
    DATA IN
    OUTPUT
    SELECT
    OUTPUT
    MUX
    PORT D PIN
    DATA OUT
    Figure 22. Port D Structure
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