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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD4135G2-A-20J

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
中文描述：
Flash在系統(tǒng)可編程外設(shè)的16位微控制器

    

    
文件頁(yè)數(shù)：
62/93頁(yè)

    

    
文件大小：
503K

    

    
代理商：
PSD4135G2-A-20J


    

    

    

	
    
    
    

    
    
	
    Preliminary Information
    PSD4000 Series
    59
    APD
    ALE
    Enable Bit
    0
    1
    1
    1
    PD Polarity
    X
    X
    1
    0
    ALE Level
    X
    Pulsing
    1
    0
    APD Counter
    Not Counting
    Not Counting
    Counting (Generates PDN after 15 Clocks)
    Counting (Generates PDN after 15 Clocks)
    Table 27.  APD Counter Operation
    The 
    PSD4000
    Functional
    Blocks
    (cont.)
    9.5.2   Other Power Saving Options
    The PSD4000 offers other reduced power saving options that are independent of the 
    Power Down Mode. Except for the SRAM Standby and CSI input features, they are
    enabled by setting bits in the PMMR0 and PMMR2 registers.
    9.5.2.1   Zero Power PLD
    The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. 
    By setting the bit to 
    “
    1
    ”
    , the Turbo mode is disabled and the PLDs consume Zero Power
    current when the inputs are not switching for an extended time of 70 ns. The propagation
    delay time will be increased after the Turbo bit is set to 
    “
    1
    ”
     (turned off) when the inputs
    change at a composite frequency of less than 15 MHz. When the Turbo bit is set to a 
    “
    0
    ”
    (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD
    ’
    s D.C.
    power, AC power, and propagation delay. Refer to AC/DC spec for PLD timings.
    Note:
     Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power
    consumption.
    9.5.2.2   SRAM Standby Mode (Battery Backup)
    The PSD4000 supports a battery backup operation that retains the contents of the SRAM 
    in the event of a power loss. The SRAM has a Vstby pin (PE6) that can be connected to
    an external battery. When V
    CC
    becomes lower than Vstby then the PSD will automatically
    connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is
    typically 0.5 μA. The SRAM data retention voltage is 2 V minimum. The battery-on 
    indicator (Vbaton) can be routed to PE7. This signal indicates when the V
    CC
    has dropped
    below the Vstby voltage and that the SRAM is running on battery power. 
    9.5.2.3   The CSI Input
    Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal 
    selects and enables the internal Flash, Boot Block, SRAM, and I/O for read or write 
    operations involving the PSD4000. A high on the CSI pin will disable the Flash memory,
    Boot Block, and SRAM, and reduce the PSD power consumption. However, the PLD and
    I/O pins remain operational when CSI is high. 
    Note:
     there may be a timing penalty when
    using the CSI pin depending on the speed grade of the PSD that you are using. See the
    timing parameter t
    SLQV
    in the AC/DC specs.
    9.5.2.4   Input Clock
    The PSD4000 provides the option to turn off the CLKIN input to the PLD AND array to 
    save AC power consumption. During Power Down Mode, or, if the CLKIN input is not 
    being used as part of the PLD logic equation, the clock should be disabled to save AC
    power. The CLKIN will be disconnected from the PLD AND array by setting bit 4 to a 
    “
    1
    ”
    in PMMR0.
    9.5.2.5   MCU Control Signals
    The PSD4000 provides the option to turn off the address input (A7-0) and input control 
    signals (CNTL0-2, ALE, and WRH/DBE) to the PLD to save AC power consumption. These 
    signals are inputs to the PLD AND array. During Power Down Mode, or, if any of them are
    not being used as part of the PLD logic equation, these control signals should be disabled
    to save AC power. They will be disconnected from the PLD AND array by setting bits 0, 2,
    3, 4, 5, and 6 to a 
    “
    1
    ”
     in the PMMR2.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
PSD4135G2-A-20JI
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4135G2-A-20M
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4135G2-A-20MI
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4135G2-A-20U
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4135G2-A-20UI
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD4135G2-A-20JI
 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4135G2-A-20M
 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4135G2-A-20MI
 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4135G2-A-20U
 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4135G2-A-20UI
 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
    
    
    
	
    	
    
    
     
     
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