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參數(shù)資料
| 型號： | PSD4135G1V-90UI |
| 廠商： | 意法半導體 |
| 英文描述： | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程外設的16位微控制器 |
| 文件頁數(shù)： | 73/93頁 |
| 文件大?。?/td> | 503K |
| 代理商： | PSD4135G1V-90UI |
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PSD4000 Series
Preliminary Information
70
-70
-90
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
ALE or AS Pulse Width
15
20
Address Setup Time
(Note 1)
4
6
ns
Address Hold Time
(Note 1)
7
8
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
8
15
ns
t
SLWL
t
DVWH
t
WHDX
t
WLWH
CS Valid to Leading Edge of WR
(Note 3)
12
15
ns
WR Data Setup Time
(Note 3)
25
35
ns
WR Data Hold Time
(Note 3)
4
5
ns
WR Pulse Width
(Note 3)
28
35
ns
t
WHAX1
Trailing Edge of WR to Address
Invalid
(Note 3)
6
8
ns
t
WHAX2
Trailing Edge of WR to DPLD
Address Input Invalid
(Note 3 and 4)
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
27
30
ns
t
AVPV
Address Input Valid to Address
Output Delay
(Note 2)
20
25
ns
Write Timing
(5 V ± 10% Versions)
NOTES:
1.
Any input used to select an internal PSD4000 function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
t
WHAX2
is Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
2.
3.
4.
Microcontroller Interface – PSD4000 AC/DC Parameters
(5V ±10% Versions)
-70
-90
Slew
Rate
(Note 1)
TURBO
OFF
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
PD
PLD Input Pin/Feedback to
PLD Combinatorial Output
20
25
Add 12
Sub 2
ns
t
ARD
PLD Array Delay
11
16
ns
PLD Combinatorial Timing
(5 V ± 10%)
NOTE:
1. Fast Slew Rate output available on Port C and F.
相關PDF資料 |
PDF描述 |
|---|---|
| PSD4135G1V-A-12B81I | CAP 0.01UF 50V 5% NP0(C0G) SMD-1825 TR-7-PL SN-NIBAR |
| PSD4135G1V-A-12J | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1825; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.177" x 0.252"; Container: Bulk; Features: Unmarked |
| PSD4135G1V-A-12JI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12M | CAP 0.01UF 100V 10% NP0(C0G) SMD-1825 TR-7-PL SN-NIBAR |
| PSD4135G1V-A-12MI | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 200V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1825; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.177" x 0.252"; Container: Bulk; Features: Unmarked |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4135G1V-A-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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