參數(shù)資料
型號(hào)： PSD412A2-C-15U
廠商： 意法半導(dǎo)體
英文描述： Low Cost Field Programmable Microcontroller Peripherals
中文描述： 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備
文件頁數(shù)： 64/123頁
文件大?。?/td> 657K
代理商： PSD412A2-C-15U
PSD4XX Famly
61
9.4 Memory Block
The PSD4XX provides EPROM memory for code storage and SRAM memory for scratch
pad usage. Chip selects for the memory blocks come from the DPLD decoding logic and
are defined by the user in the PSDsoft Software. Figure 32 shows the organization of the
Memory Block.
The PSD4XX family uses Zero-power memory techniques that place memory into Standby
Mode between MCU accesses. The memory becomes active briefly after an address
transition, then delivers new data to the outputs, latches the outputs, and returns to standby.
This is done automatically and the designer has to do nothing special to benefit from this
feature. Both the EPROM and SRAM have this feature.
9.4.1 EPROM
The PSD4XX provides three EPROM densities: 256Kbit, 512Kbit, or 1Mbit. The EPROM
is divided into four 8K, 16K or 32K byte blocks. Each block has its own chip select signals
(ES0 – ES3). The EPROM can be configured as 32K x 8, 64K x 8 or 128K x 8 for
microcontrollers with an 8-bit data bus. For 16-bit data buses, the EPROM is configured as
16K x 16, 32K x 16 or 64K x 16.
9.4.2 SRAM
The SRAM has 16Kbits of memory, organized as 2K x 8 or 1K x 16. The SRAM is enabled
by chip select signal RS0 from the DPLD. The SRAM has a battery back-up (STBY) mode.
This back-up mode is invoked when the V
CC
voltage drops under the Vstdby voltage by
approximately 0.7 V. The Vstdby voltage is connected only to the SRAM and cannot be
lower than 2.7 volts.
9.4.3 Memory Select Map
The EPROM and SRAM chip select equations are defined in the ABEL file in terms of
address and other DPLD inputs. The memory space for the EPROM chip select
(ES0 – ES3) should not be larger than the EPROM block (8KB, 16KB, or 32KB) it is
selecting.
The following rules govern how the internal PSD4XX memory selects/space are defined:
J
The EPROM blocks address space cannot overlap
J
SRAM, internal I/O and Peripheral I/O space cannot overlap
J
SRAM, internal I/O and Peripheral I/O space can overlap EPROM space, with
priority given to SRAM or I/O. The portion of EPROM which is overlapped
cannot be accessed.
The Peripheral I/O space refers to memory space occupied by peripherals when Port A is
configured in the Peripheral I/O Mode.
The PSD4XX
Architecture
(cont.)
相關(guān)PDF資料
PDF描述
PSD403A2-C-15J DIODE SOT404 SCHOTTKY BARRIER RECTIFIER DIODE
PSD413A2-C-15J RECTIFIER FAST-RECOVERY DUAL COMMON-CATHODE 16A 200V 100A-ifsm 0.975V-vf 30ns 5uA-ir D2PAK 800/REEL-13
PSD403A2-C-15L RECTIFIER FAST-RECOVERY SINGLE 1A 200V 40A-ifsm 0.875V-vf 25ns 2uA-ir SMB 5K/REEL-13
PSD413A2-C-15L RECTIFIER FAST-RECOVERY SINGLE 1A 400V 35A-ifsm 1.25V-vf 50ns 5uA-ir SMB 5K/REEL-13
PSD403A2-C-15U RECTIFIER FAST-RECOVERY SINGLE 1A 600V 35A-ifsm 1.25V-vf 50ns 5uA-ir SMB 5K/REEL-13
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD412A2-C-70J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD412A2-C-70L 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD412A2-C-70U 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD412A2-C-90JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD412A2-C-90UI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
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