• 參數(shù)資料
    型號: PSD412A1-15J
    英文描述: 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-205AF package; JANS Certified version of the IRHF7130
    中文描述: 現(xiàn)場可編程外圍
    文件頁數(shù): 53/123頁
    文件大小: 657K
    代理商: PSD412A1-15J
    PSD4XX Famly
    50
    Port Mode
    Port A
    Port B
    Port C
    Port D
    Port E
    Standard MCU I/O
    Yes
    Yes
    Yes
    Yes
    Yes
    PLD I/O
    Yes
    Yes
    Input Only
    *
    Input Only
    *
    Yes
    *
    Address Out
    Yes
    Yes
    Yes
    Yes
    Yes
    Address In
    Yes
    Yes
    **
    Yes
    **
    Yes
    **
    Data Port
    Yes
    Yes
    Alternate Function In
    Yes
    Peripheral I/O
    Yes
    Open Drain
    Yes
    Yes
    *
    PSD4XXA2 and ZPSD4XXA2 Only.
    **
    For external decoding. Cannot be latched by ALE
    9.3.7 Peripheral I/O
    This mode enables the microcontroller to read or write to a peripheral though Port A. When
    there is no read/write operation, Port A is tri-stated. One of the applications of Peripheral
    I/O is in a DMA based design.
    J
    Configuration
    1.Declare the pins used as pheripheral I/O in the ABEL file.
    2.Write logic equations for PSEL0 and PSEL1.
    3.Write a “1” to the PIO bit in the VM Register to activate the Peripheral I/O operation.
    See the section on Peripheral I/O for a detailed description.
    9.3.8 Open Drain Outputs
    This mode enables the user to configure Ports C and D pins as open drain outputs. CMOS
    output is the default configuration. Writing “1” to the corresponding bit in the Open Drain
    Register changes the pin to open drain output.
    Table 12. Operating Modes of the I/OPorts
    Table 12 summarizes the operating modes of the I/O ports. Not all the functions are
    available to every port.
    The PSD4XX
    Architecture
    (cont.)
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    相關(guān)代理商/技術(shù)參數(shù)
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    PSD412A1-15UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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