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參數(shù)資料
| 型號： | PSD411A1-C-70U |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125 |
| 中文描述： | 低成本現(xiàn)場可編程微控制器外圍設(shè)備 |
| 文件頁數(shù)： | 60/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD411A1-C-70U |
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9.3.12 Port C and Port D – Functionality and Structure
Ports C and D are identical in function and structure and each can be configured to perform
one or more of the following operating modes:
J
Standard MCU I/O Mode
J
PLD Input – direct input to ZPLD
(PSD4XXA2 and ZPSD4XXA2 Only)
J
Address Out – latched address outputs
– Port C: A[0-7] are assigned to pins PC[0-7]
– Port D: A[0-7] for 8-bit multiplexed bus or A[8-15] for 16-bit multiplexed
bus are assigned to pins PD0-7]
J
Data Port
– Port C: D[0-7] for 8-bit non-multiplexed bus
– Port D: D[8-15] for 16-bit non-multiplexed bus
J
Open Drain – select CMOS or Open Drain driver
Figures 29 and 30 show the structure of a Port C or D pin. If the pin is configured as output
port, the multiplexer selects one of the two inputs as output. If the pin is configured as input,
the input connects to :
J
Data In Register as input in the Standard MCU I/O Mode
or
J
ZPLD input (PSD4XXA2 and ZPSD4XXA2 Only)
9.3.13 Port E – Functionality and Structure
Port E can be configured to perform one or more of the following functions:
J
Standard MCU I/O Mode
J
PLD I/O (PSD4XXA2 and ZPSD4XXA2 Only)
J
Address Out – latched address lines A[0-7] are assigned to pins PE[0-7]
J
Alternate Function In – in this mode, the inputs to Port E pins are:
–
PE0
BHE or PSEN or WRH or UDS or SIZ0
–
PE1
– ALE
–
PE7
APD CLK :clock input for Automatic Power Down Counter
Figure 31 shows the structure of a Port E pin. The Control Logic block selects one of four
sources through the multiplexer for pin output. If the pin is configured as input, the input
goes to:
J
Data In Register as input in Standard MCU I/O Mode
or
J
PE Macrocell as PLD input (PSD4XXA2 and ZPSD4XXA2 Only)
or
J
Alternate Function In
PSD4XX Famly
57
The PSD4XX
Architecture
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD411A1-C-90JI | High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125 |
| PSD411A1-C-90UI | High Speed CMOS Logic Hex Schmitt-Triggered Inverters 14-PDIP -55 to 125 |
| PSD411A2-C-70J | High Speed CMOS Logic Hex Schmitt-Triggered Inverters 14-SOIC -55 to 125 |
| PSD411A2-C-70L | High Speed CMOS Logic Hex Schmitt-Triggered Inverters 14-SOIC -55 to 125 |
| PSD411A2-C-70U | High Speed CMOS Logic Hex Schmitt-Triggered Inverters 14-SOIC -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD411A1-C-90JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD411A1-C-90UI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD411A2 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD411A2-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD411A2-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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