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參數(shù)資料
| 型號： | PSD402A1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現(xiàn)場可編程微控制器外圍設(shè)備 |
| 文件頁數(shù)： | 51/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD402A1 |
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PSD4XX Famly
48
9.3 I/OPorts
There are 5 programmable 8-bit I/O ports: Port A, Port B, Port C, Port D and Port E. These
ports all have multiple operating modes, depending on the configuration. Some of the basic
functions are providing input/output for the ZPLD, or can be used for standard I/O. Each
port pin is individually configurable, thus enabling a single 8-bit port to perform multiple
functions. The I/O ports occupy 256 bytes of memory space as defined by “CSIOP”. Refer
to the System Configuration section for I/O register address offset.
To set up the port configuration the user is required to:
1. Define I/O Port Chip Select (CSIOP) in the ABEL file.
2. Initialize certain port configuration registers in the user’s program and/or
3. Specify the configuration in the PSD4XX PSDsoft Software.
4. Unused input pins should be tied to V
CC
or GND.
The following is a description of the operating modes of the I/O ports. The functions of the
port registers are described in later sections.
9.3.1 Standard MCUI/O
The Standard MCU I/O Mode provides additional I/O capability to the microcontroller. In this
mode, the ports can perform standard I/O functions such as sensing or controlling various
external I/O devices. Operation options of this mode are as follows:
J
Configuration
1.Declare pins or signals which are used as I/O in the ABEL file.
2.Set the bit or bits in the Control Register to "1".
3.
As Output Port
– Write output data to Data Out Register
– Set Direction Register to output mode
4.
As Input Port
– Set Direction Register to input mode
– Read input from Data In Register
The port remains an output or input port as long as the Direction Register is not changed.
9.3.2 PLDI/O
The PLD I/O mode enables the port to be configured as an input to the ZPLD, or as an
output from the GPLD macrocell. The output can be tri-stated with a control signal defined
by a product term from the ZPLD. This mode is configured by the user in the PSD4XX
PSDsoft Software, and is enabled upon power up. For a detailed description, see the
section on the ZPLD.
J
Configuration
1.Declare pins or signals in the ABEL file (PSDsoft).
2.Write logic equations in the ABEL file.
3.PSD Compiler maps the PLD functions to the PSD.
The PSD4XX
Architecture
(cont.)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PSD402A1-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD402A1-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD402A1-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD402A1-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD402A1-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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