
2-73
Key Features
Programmable Peripheral
PSD302
Field-Programmable Microcontroller Peripheral 
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 Single Chip Programmable Peripheral for Microcontroller-based Applications
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 19 Individually Configurable I/O pins that can be used as:
— Microcontroller I/O port expansion
— Programmable Address Decoder (PAD) I/O 
— Latched address output
— Open drain or CMOS
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 Two Programmable Arrays (PAD A & PAD B)
— Total of 40 Product Terms and up to 16 Inputs and 24 Outputs 
— Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging
— Logic replacement
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 “No Glue” Microcontroller Chip-Set
— Built-in address latches for multiplexed address/data bus
— Non-multiplexed address/data bus mode
— Selectable 8 or 16 bit data bus width
— ALE and Reset polarity programmable
— Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS
— BHE pin for byte select in 16-bit mode
— PSEN pin for 8051 users
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 Built-In Page Logic
— To Expand the Address Space of Microcontrollers with Limited Address 
Space Capabilities 
— Up to 16 pages
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 512 Kbits of UV EPROM
— Configurable as 64K x 8 or as 32K x 16
— Divides into 8 equal mappable blocks for optimized mapping
— Block resolution is 8K x 8 or 4K x 16
— 70 ns EPROM access time, including input latches and PAD address decoding.
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 16 Kbit Static RAM
— Configurable as 2K x 8 or as 1K x 16
— 70 ns SRAM access time, including input latches and PAD address decoding
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 Address/Data Track Mode
— Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other 
Microcontrollers or a Host Processor
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 CMiser-Bit
— Programmable option to further reduce power consumption
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 Built-In Security
— Locks the PSD302 and PAD Decoding Configuration
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 Available in a Choice of Packages
— 44 Pin PLDCC, CLDCC and TQFP
— 52 Pin PQFP
— 44 Pin CPGA
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 Simple Menu-Driven Software: Configure the PSD302 on an IBM PC
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 Pin and Function Compatible with the PSD301/301L, PSD303/303L and 
PSD304R/304RL