參數(shù)資料
型號(hào)： PSB21525-H
英文描述： ?High-Level Serial Communication Controller Extended?
中文描述： ？高級(jí)別串行通信控制器擴(kuò)展？
文件頁(yè)數(shù)： 50/317頁(yè)
文件大?。?/td> 3334K
代理商： PSB21525-H
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PSB 2115
PSF 2115
Functional Description
Semiconductor Group
50
11.97
For transparent frames, the whole frame including address and control field must be
written to the XFIFOD.
The transmission of
I
frames
is possible only if the IPAC is operating in the auto mode.
The address and control field is autonomously generated by the IPAC and appended to
the frame, only the data in the information field must be written to the XFIFOD.
If a 2-byte address field has been selected, the IPAC takes the contents of the XAD 1
register to build the high byte of the address field, and the contents of the XAD 2 register
to build the low byte of the address field.
Additionally the C/R bit (bit 1 of the high byte address, as defined by LAPD protocol) is
set to “1” or “0” depending on whether the frame is a command or a response.
In the case of a 1-byte address, the IPAC takes either the XAD 1 or XAD 2 register to
differentiate between command or response frame (as defined by X.25 LAPB).
The control field is also generated by the IPAC including the receive and send sequence
number and the poll/final (P/F) bit. For this purpose, the IPAC internally manages send
and receive sequence number counters.
In the auto mode, S frames are sent autonomously by the IPAC. The transmission of
U frames, however, must be done by the CPU. U frames must be sent as transparent
frames (XTF), i.e. address and control field must be defined by the CPU.
Once the data transmission has been initiated by command (XTF or XIF), the data
transfer between CPU and IPAC is controlled by interrupts.
The IPAC repeatedly requests another data packet or block by means of an XPR
interrupt, every time no more than 32 bytes are stored in the XFIFOD.
The processor can then write further data to the XFIFOD and enable the continuation of
frame transmission by issuing an XIF/XTF command.
If the data block which has been written last to the XFIFOD completes the current frame,
this must be indicated additionally by setting the XME (Transmit Message End)
command bit. The IPAC then terminates the frame properly by appending the CRC and
closing flag.
If the CPU fails to respond to an XPR interrupt within the given reaction time, a data
underrun condition occurs (XFIFOD holds no further valid data). In this case, the IPAC
automatically aborts the current frame by sending seven consecutive “ones” (ABORT
sequence).
The CPU is informed about this via an XDU (Transmit Data Underrun) interrupt.
It is also possible to abort a message by software by issuing an XRES (Transmitter
RESet) command, which causes an XPR interrupt.
After an end of message indication from the CPU (XME command), the termination of
the transmission operation is indicated differently, depending on the selected message
transfer mode and the transmitted frame type.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSB21525-N 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:?High-Level Serial Communication Controller Extended?
PSB21525NV2.1 制造商:Rochester Electronics LLC 功能描述:- Bulk
PSB21525-NV2.1 制造商:Siemens 功能描述:2 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC44
PSB21525NV2.1-HSCXTE 制造商:Rochester Electronics LLC 功能描述:- Bulk
PSB21553E 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Infineon VoIP engine with Embedded MIPS processor. 3 port Ethernet switch and Acoustic Echo Cancellation
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