
PSB 2115
PSF 2115
Operational Description
Semiconductor Group
171
11.97
MOS Interrupt Logic
In the case of IOM-2 non-terminal timing modes only one MONITOR channel is handled
and MOR1 and MOX1 are unused.
The interrupt logic is different for MONITOR channel 0 and channel 1:
 MONITOR channel 0
The MONITOR Data Receive 
MDR0
 and the MONITOR channel End of Reception
MER0 
interrupt status have two enable bits, MONITOR Receive interrupt Enable
(
MRE0
) and MR bit Control (
MRC0
). 
The MONITOR channel Data Acknowledged 
MDA0
 and MONITOR channel Data Abort
MAB0
 interrupt status bits have a common enable bit MONITOR Interrupt Enable 
MIE0
.
MRE0
 prevents the occurrence of 
MDR0
 status, including when the first byte of a packet
is received. When 
MRE0
 is active (1) but 
MRC0
 is inactive, the 
MDR0
 interrupt status is
generated only for the first byte of a receive packet. When both 
MRE0
 and 
MRC0
 are
active, 
MDR
 is always generated and all received MONITOR bytes - marked by a 1-to-0
transition in MX bit - are stored. (Additionally, an active 
MRC0
 enables the control of the
MR handshake bit according to the MONITOR channel protocol.)
 MONITOR channel 1
The MONITOR Data Receive interrupt status 
MDR1
 has two enable bits, MONITOR
Receive interrupt Enable (
MRE1
) and MR bit Control (
MRC1
). The MONITOR channel
End of Reception 
MER1
, MONITOR channel Data Acknowledged 
MDA1
 and MONITOR
channel Data Abort 
MAB1
 interrupt status bits have a common enable bit MONITOR
Interrupt Enable 
MIE1
.
MRE1
 prevents the occurrence of 
MDR1
 status, including when the first byte of a packet
is received. When 
MRE1
 is active (1) but 
MRC1
 is inactive, the 
MDR1
 interrupt status is
generated only for the first byte of a receive packet. When both 
MRE1
 and 
MRC1
 are
active, 
MDR1
 is always generated and all received MONITOR bytes - marked by a 1-
to-0 transition in MX bit - are stored. (Additionally, an active 
MRC1
 enables the control
of the MR handshake bit according to the MONITOR channel protocol.)