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參數(shù)資料
| 型號： | PS395ACWG |
| 英文描述： | SPST Analog Switch |
| 中文描述： | SPST模擬開關(guān) |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 363K |
| 代理商： | PS395ACWG |
10
PS8463C 03/07/01
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PS395A
Low On-Resistance 8-Channel 17V,
Detailed Description
Basic Operation
The PS395As interface can be thought of as an 8-bit shift register
controlled by CS (Figure 7). While CS is low, input data appearing
at DIN is clocked into the shift register synchronously with SCLKs
rising edge. The data is an 8-bit word, each bit controlling one of
eight switches in the PS395A. DOUT is the shift registers output,
with data appearing synchronously with SCLKs falling edge. Data
at DOUT is simply the input data delayed by eight clock cycles.
When shifting the input data, D7 is the first bit in and out of the
shift register. While shifting data, the switches remain in their pre-
vious configuration. When the eight bits of data have been shifted
in, CS is driven high. This updates the new switch configuration
and inhibits further data from entering the shift register. Transi-
tions at DIN and SCLK have no effect when CS is high, and DOUT
holds the first input bit (D7) at its output.
More or less than eight clock cycles can be entered during the CS
low period. When this happens, the shift register will contain only
the last eight serial data bits, regardless of when they were en-
tered. On the rising edge of CS, all the switches will be set to the
corresponding states.
The PS395As three-wire serial interface is compatible with SPI,
QSPI, and Microwire standards. If inter-facing with a Motorola
processor serial interface, set CPOL = 0. The PS395A is considered
a slave device (Figures 2 and 7). Upon power-up, the shift register
contains all zeros, and all switches are off.
The latch that drives the analog switch is updated on the rising
edge of CS, regardless of SCLKs state. This meets all the SPI and
QSPI requirements.
Daisy Chaining
For a simple interface using several PS395As, daisy chain the
shift registers as shown in Figure 5. The CS pins of all devices are
connected together, and a stream of data is shifted through the
PS395As in series. When CS is brought high, all switches are
updated simultaneously. Additional shift registers may be included
anywhere in series with the PS395 data chain.
t
CSH0
SCLK
DIN
DOUT
COM OUT
t
CSS
t
CL
t
DS
t
DH
t
DO
t
CSH1
tOFF
t
CSH2
t
CLL
t
CH
Figure 1. Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PS395AEPG | SPST Analog Switch |
| PS395AEWG | SPST Analog Switch |
| PS395CWG | ANALOG SWITCH|OCTAL|SPST|CMOS|SOP|24PIN|PLASTIC |
| PS395ENG | ANALOG SWITCH|OCTAL|SPST|CMOS|DIP|24PIN|PLASTIC |
| PS395EWG | ANALOG SWITCH|OCTAL|SPST|CMOS|SOP|24PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PS395AEPG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPST Analog Switch |
| PS395AEWG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPST Analog Switch |
| PS395CNB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ANALOG SWITCH|OCTAL|SPST|CMOS|DIP|24PIN|PLASTIC |
| PS395CWG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ANALOG SWITCH|OCTAL|SPST|CMOS|SOP|24PIN|PLASTIC |
| PS395ENG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ANALOG SWITCH|OCTAL|SPST|CMOS|DIP|24PIN|PLASTIC |
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