參數(shù)資料
型號: PS21563
元件分類: 運(yùn)動控制電子
英文描述: AC MOTOR CONTROLLER, 20 A, XMA35
封裝: DIP-35
文件頁數(shù): 2/9頁
文件大?。?/td> 113K
代理商: PS21563
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21563
TRANSFER-MOLD TYPE
INSULATED TYPE
Jul. 2003
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0
s.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Drive circuit
Protection circuit
W
V
U
B
C
VNC
CIN
A
P
N1
N
C
R
Shunt Resistor
External protection circuit
DIP-IPM
L-side IGBTS
H-side IGBTS
SC Protection
Trip Level
IC (A)
tw (
s)
2
0
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
Collector current
waveform
(Note 1)
(Note 2)
Z
AC line input
C
Drive circuit
CBU–
CBU+
CBV–
CBV+
CBW–
CBW+
(15V line)
(5V line)
(Note 1, 2)
VD
VNC
W
V
U
Input signal
conditioning
Level shifter
Drive circuit
Protection
circuit (UV)
Input signal
conditioning
Input signal
conditioning
Input signal conditioning
Fo logic
Protection
circuit
circuit (UV)
Protection
circuit (UV)
Control supply
Under-Voltage
protection
Drive circuit Drive circuit
FO
CFO
P
N1
N
Fault output (5V line)
(Note 3, 5)
High-side input (PWM)
(5V line)
(Note 1,2)
Low-side input (PWM)
(Note 6)
DIP-IPM
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
C2
C1
C1 : Tight tolerance, temp-compensated electrolytic type
C2 : 0.22~2
F R-category ceramic capacitor for noise filtering.
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
Note1:
Input logic is high-active. There is a 2.5k
(min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
2:
By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 8)
3:
This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10k
resistance.
(see also Fig. 8)
4:
The wiring between the power DC link capacitor and the PN1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22
F, high voltage type) is recommended to be mounted close to
these PN1 DC power input pins.
5:
Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF
→ tFO=1.8ms (Typ.))
6:
High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
7:
The terminal VNO should be connected to the terminal N outside of DIP-IPM.
H-side IGBTS
L-side IGBTS
(Note 4)
(Note 7)
Fig. 3
Inrush current
limiter circuit
Level shifter Level shifter
Protection
CIN
VNO
AC line output
M
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
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