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參數資料
| 型號： | PS12014-A |
| 廠商： | Powerex Power Semiconductors |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-C-26482, Series I; Body Material:Aluminum Alloy; Series:MS3124; No. of Contacts:12; Connector Shell Size:14; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle RoHS Compliant: No |
| 中文描述： | 平性基地型絕緣型 |
| 文件頁數： | 5/6頁 |
| 文件大?。?/td> | 393K |
| 代理商： | PS12014-A |
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12014-A
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
SC delay time
Short circuit sensing signal VS
Error output FO1
Gate signal Vo of each phase
upper arm(ASIPM internal)
Input signal VCIN of each phase
upper arm
0V
Input signal VCIN(p) of each phase upper arm
Input signal VCIN(n) of each phase lower arm
Gate signal Vo(p) of each phase upper arm
(ASIPM internal)
Gate signal Vo(n) of each phase upper arm
(ASIPM internal)
Error output FO1
VCH(5
s)
VCH(505
s)
0V
VC
500
s
rCH=
VCH(505
s)-VCH(5s)
VCH(5
s)
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5
s delayed point.
200
–200
Analogue output signal
data hold range
1
2
3
4
5
400
300
100
0
–100
–300
–400
0
VC+(200%)
VC0
VC
–(200%)
V
C
(V)
VC+
VC–
min
max
Real load current peak value.(%)(Ic=Io! 2)
VDH=15V
VDL=5V
TC=
–20~100C
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING
LINEARITY
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “FO” signal is outputted. After an “input
interlock” operation the circuit is latched. The “FO” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
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