參數(shù)資料
型號(hào): PR31500
廠商: NXP Semiconductors N.V.
英文描述: Poseidon Embedded Processor(Poseidon 嵌入式處理器)
中文描述: 海神嵌入式處理器(波塞冬嵌入式處理器)
文件頁(yè)數(shù): 5/24頁(yè)
文件大?。?/td> 276K
代理商: PR31500
Philips Semiconductors
Preliminary specification
MIPS
PR31500
Poseidon embedded processor
1996 Sep 24
5
IR Module
IR consumer mode
allows control of consumer electronic devices such as stereos,
TVs, VCRs, etc.
programmable pulse parameters
external analog LED circuitry
IRDA communication mode
allows communication with other IRDA devices such as FAX
machines, copiers, printers, etc.
supported by UART module within PR31500
external analog receiver preamp and LED circuitry
data rate = up to 115 Kbps at 1 meter
IR FSK communication mode
supported by UART module within PR31500
external analog IR chip(s) perform frequency modulation to
generate the desired IR communication mode protocol
data rate = up to 36000 bps at 3 meters
carrier detect state machine
periodically enables IR receiver to check if a valid carrier is
present
Power Module
power-down modes for individual internal peripheral modules
serial (SPI port) power supply control interface supported
power management state machine has 4 states: RUNNING,
DOZING, SLEEP, and COMA
Serial Interconnect Bus (SIB) Module
PR31500 contains holding and shift registers to support the serial
interface to the UCB1100 and/or other optional codec devices
interface compatible with slave mode 3 of Crystal CS4216 codec
synchronous, frame-based protocol
PR31500 always master source of clock and frame frequency and
phase; programmable clock frequency
each SIB frame consists of 128 clock cycles, further divided into 2
subframes or words of 64 bits each (supports up to 2 devices
simultaneously)
independent DMA support for audio receive and transmit, telecom
receive and transmit
supports 8-bit or 16-bit mono telecom formats
supports 8-bit or 16-bit mono or stereo audio formats
independently programmable audio and telecom sample rates
CPU read/write registers for subframe control and status
System Peripheral Interface (SPI) Module
provides interface to SPI peripherals and devices
full-duplex, synchronous serial data transfers (data in, data out,
and clock signals)
PR31500 supplies dedicated chip select and interrupt for an SPI
interface serial power supply
8-bit or 16-bit data word lengths for the SPI interface
programmable SPI baud rate
Timer Module
Real Time Clock (RTC) and Timer
40-bit counter (30.517
μ
sec granularity);
maximum uninterrupted time = 388.36 days
40-bit alarm register (30.517
μ
sec granularity)
16-bit periodic timer (0.868
μ
sec granularity);
maximum timeout = 56.8 msec
interrupts on alarm, timer, and prior to RTC roll-over
UART Module
2 independent full-duplex UARTs
programmable baud rate generator
UART-A port used for serial control interface to external IR
module
UART-B port used for general purpose serial control interface
UART-A and UART-B DMA support for receive and transmit
Video Module
bit-mapped graphics
supports monochrome, grey scale, or color modes
time-based dithering algorithm for grey scale and color modes
supports multiple screen sizes
supports split and non-split displays
variable size and relocatable video buffer
DMA support for fetching image data from video buffer
Little/Big Endian Configuration
The PR31500 can be configures as a Big Endian or as a Little
Endian processor based on the /LB endian pin at power-up.
The byte ordering is as follows:
LITTLE ENDIAN
D[31:24]
D[23:16]
D[15:8]
D[7:0]
/CAS3
/CAS2
/CAS1
/CAS0
BIG ENDIAN
D[7:0]
D[15:8]
D[23:16]
D[31:24]
/CAS0
/CAS1
/CAS2
/CAS3
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