參數(shù)資料
型號(hào)： PPC440SPE-RNB533C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SPe Embedded Processor
中文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA675
封裝： 27 X 27 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-675
文件頁數(shù)： 61/80頁
文件大?。?/td> 572K
代理商： PPC440SPE-RNB533C
PowerPC 440SPe Embedded Processor
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
AMCC Proprietary
61
Input Max Allowable Overshoot (3.3V LVTTL)
VIMAO
+3.9
V
Input Max Allowable Undershoot (3.3V LVTTL)
V
IMAU
-0.6
V
Output Max Allowable Overshoot (3.3V LVTTL)
VOMAO
+3.9
V
Output Max Allowable Undershoot (3.3V LVTTL)
V
OMAU3
-0.6
V
Case Temperature
T
C
0
+95
°
C
6
Notes:
1. PCI-X drivers meet PCI-X specifications.
2. SV
REF
= SV
DD
/2
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440SPe. See “Absolute Maximum Ratings” on page 58.
4. During chip power-up, OVDD should begin to ramp before VDD. External voltage should not be applied to the chip I/O pins before
OVDD is applied to the chip. A power-down cycle should complete (OVDD and VDD should both be below 0.4V) before a new power
up cycle is started.
5. LPDL is least positive down level; MPUL is most positive up level.
6. Case temperature, T
C
, is measured at top center of case surface with device soldered to circuit board.
Table 10. Input Capacitance
Parameter
Symbol
Maximum
Unit
Notes
Group 1 (2.5V SSTL I/O)
CIN1
5.7
pF
Group 2 (3.3V LVTTL I/O)
CIN2
6.8
pF
Group 3 (PCI-X I/O)
CIN3
5.1
pF
Group 4 (Receivers)
CIN4
6.7
pF
Group 5 (3.3V tolerant CMOS I/O)
CIN5
2.6
pF
Table 9. Recommended DC Operating Conditions (Sheet 3 of 3)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
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