參數(shù)資料
PowerPC 440SP Embedded Processor
8
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
Table 2. DCR Address Map (4KB of Device Configuration Registers)
Function
Start Address
End Address
Size
Total DCR Address Space
1
000
3FF
1KW (4KB)
1
By function:
Reserved
000
00B
12W
Clocking Power On Reset
00C
00D
2W
System DCRs
00E
00F
2W
Memory Controller
010
011
2W
External Bus Controller
012
013
2W
Reserved
014
01F
12W
SRAM
020
02F
16W
L2 Controller
030
03F
16W
Memory Queue
040
04F
16W
Reserved
050
05F
16W
I2O/DMA
060
07F
32W
PLB
080
08F
16W
PLB to OPB Bridge Out
090
09F
16W
Reserved
0A0
0AF
16W
Reserved
0B0
0B1
2W
Reserved
0B2
0BF
14W
Interrupt Controller 0
0C0
0CF
16W
Interrupt Controller 1
0D0
0DF
16W
Power Management
0E0
0E7
8W
Reserved
0E8
17F
152W
Ethernet MAL
180
1FF
128W
Reserved
200
3FF
512W
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a sin-
gle 32-bit (word) register. One KW (1024W) equals 4KB (4096 bytes).
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