- 您現(xiàn)在的位置：買賣IC網 > PDF目錄368097 > PPC440GX-3FF667C (APPLIEDMICRO INC) Power PC 440GX Embedded Processor PDF資料下載
參數資料
| 型號： | PPC440GX-3FF667C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Power PC 440GX Embedded Processor |
| 中文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, PBGA552 |
| 封裝： | 25 X 25 MM, PLASTIC, FBGA-552 |
| 文件頁數： | 89/93頁 |
| 文件大?。?/td> | 794K |
| 代理商： | PPC440GX-3FF667C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁當前第89頁第90頁第91頁第92頁第93頁
440GX – Power PC 440GX Embedded Processor
AMCC
89
Revision 1.15 – August 30, 2007
Data Sheet
Initialization
The PPC440GX provides the option for setting initial parameters based on default values or by reading them from
a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered
by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440GX start-up. The actual capture instant is the nearest SysClk edge before the
deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. They are used for strap functions only during reset. Following
reset they are used for normal functions.
The following table lists the strapping pins along with their functions and strapping options:
Serial EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device
connected to the IIC0 port. At the de-assertion of SysReset, if the bootstrap controller is enabled, the PPC440GX
sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,
SDR0_SDSTP2, and SDR0_SDSTP3 registers accordingly.
The initialization settings and their default values are covered in detail in the
PowerPC 440GX Embedded
Processor User’s Manual
.
Strapping Pin Assignments
Function
Option
Ball Strapping
V24
(UART0_DCD)
V02
(UART0_DSR)
L07
(GMC1TxEr)
Serial device is disabled. Each of the four options (A–
D) is a combination of boot source, boot-source width,
and clock frequency specifications. Refer to the IIC
Bootstrap Controller chapter in the
PPC440GX
Embedded Processor User’s Manual
for details.
A
0
0
0
B
0
x
1
C
0
1
0
D
1
0
0
Serial device is enabled. The option being
selected is the IIC0 slave address that will
respond with strapping data.
0x54
1
0
1
0x50
1
1
1
相關PDF資料 |
PDF描述 |
|---|---|
| PPC440GX-3FF667E | Power PC 440GX Embedded Processor |
| PPC440GX-3RF400C | Power PC 440GX Embedded Processor |
| PPC440GX-3RF533C | Power PC 440GX Embedded Processor |
| PPC440GX-3RF533CZ | Power PC 440GX Embedded Processor |
| PPC440GX-3RF533E | Power PC 440GX Embedded Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PPC440GX-3FF667CZ | 制造商:AppliedMicro 功能描述:MPU 440GX RISC 32BIT 0.13UM 667MHZ 3.3V 552FCBGA - Tape and Reel |
| PPC440GX-3FF667E | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 440GX Embedded Processor |
| PPC440GX-3FF800CZ | 制造商:AppliedMicro 功能描述:MPU 440GX RISC 32BIT 0.13UM 800MHZ 3.3V 552FCBGA - Tape and Reel |
| PPC440GX-3NF533C | 制造商:AppliedMicro 功能描述:MPU 440GX RISC 32BIT 0.13UM 533MHZ 3.3V 552FCBGA - Trays |
| PPC440GX-3NF533CZ | 制造商:AppliedMicro 功能描述:MPU 440GX RISC 32BIT 0.13UM 533MHZ 3.3V 552FCBGA - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。