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參數(shù)資料
| 型號： | PPC440GX-3FF533C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Power PC 440GX Embedded Processor |
| 中文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA552 |
| 封裝： | 25 X 25 MM, PLASTIC, FBGA-552 |
| 文件頁數(shù)： | 78/93頁 |
| 文件大小： | 794K |
| 代理商： | PPC440GX-3FF533C |
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440GX – Power PC 440GX Embedded Processor
78
AMCC
Revision 1.15 – August 30, 2007
Data Sheet
DDR SDRAM I/O Specifications
The DDR SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the
same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Note:
MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR program-
ming register. In a typical system, users advance MemClkOut by 90
°
. This depends on the specific applica-
tion and requires a thorough understanding of the memory system in general (refer to the DDR SDRAM
controller chapter in the
PowerPC 440GX User’s Manual
).
In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and
MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90
°
. Advancing MemClkOut0 by 90
°
creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to
MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal.
The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths.
Values are calculated over best case and worst case processes with speed, temperature, and voltage as follows:
Best Case = Fast process, -40
°
C, +1.6V
Worst Case = Slow process, +85
°
C, +1.4V
Note:
In all the following DDR tables and timing diagrams,
minimum
values are measured under
best
case condi-
tions and
maximum
values are measured under
worst
case conditions.
The signals are terminated as indicated in the figure below for the DDR timing data in the following sections.
DDR SDRAM Simulation Signal Termination Model
10pF
10pF
MemClkOut0
MemClkOut0
120
Ω
50
Ω
Addr/Ctrl/Data/DQS
V
TT
= SV
DD
/2
PPC440GX
30pF
Note:
This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is
not
a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
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| PPC440GX-3FF667C | Power PC 440GX Embedded Processor |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440GX-3FF533CZ | 制造商:AppliedMicro 功能描述:MPU 440GX RISC 32BIT 0.13UM 533MHZ 3.3V 552FCBGA - Tape and Reel |
| PPC440GX-3FF533E | 制造商:AppliedMicro 功能描述: |
| PPC440GX-3FF667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 440GX Embedded Processor |
| PPC440GX-3FF667CZ | 制造商:AppliedMicro 功能描述:MPU 440GX RISC 32BIT 0.13UM 667MHZ 3.3V 552FCBGA - Tape and Reel |
| PPC440GX-3FF667E | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 440GX Embedded Processor |
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