
Revision 1.16 – July 19, 2006
AMCC Proprietary
1
440GR
Power PC 440GR Embedded Processor
Preliminary Data Sheet
Features
PowerPC 440 processor core operating up to
667MHz with 32KB I-cache and D-cache with
parity checking.
Selectable processor:bus clock ratios of N:1, N:2.
Dual bridged Processor Local Buses (PLBs) with
64- and 128-bit widths.
Double Data Rate (DDR) Synchronous DRAM
(SDRAM) interface operating up to 133MHz with
ECC.
DMA support for external peripherals, internal
UART and memory.
PCI V2.2 interface (3.3V only). Thirty-two bits at
up to 66MHz.
Programmable interrupt controller supports
interrupts from a variety of sources.
Programmable General Purpose Timers (GPT).
Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are MII,
RMII, and SMII with packet reject.
Up to four serial ports (16750 compatible UART).
External peripheral bus (16-bit data) for up to six
devices with external mastering.
Two IIC interfaces (one with boot parameter read
capability).
NAND Flash interface.
SPI interface.
General Purpose I/O (GPIO) interface.
JTAG interface for board level testing.
Boot from PCI memory, NOR Flash on the
extrenal peripheral bus, or NAND Flash on the
NAND Flash interface.
Available in RoHS compliant lead-free package.
Description
Designed specifically to address high-end embedded
applications, the PowerPC 440GR (PPC440GR)
provides a high-performance, low- power solution that
interfaces to a wide range of peripherals and
incorporates on-chip power management features.
This chip contains a high-performance RISC
processor, DDR SDRAM controller, PCI bus interface,
control for external ROM and peripherals, DMA with
scatter-gather support, Ethernet ports, serial ports, IIC
interfaces, SPI interface, NAND Flash interface, and
general purpose I/O.
Technology: CMOS Cu-11, 0.13
μm.
Package: 35mm, 456-ball enhanced plastic ball grid
array (E-PBGA).
Typical power (estimated): Less than 2.5W at
533MHz, 2.3W at 400MHz.
Supply voltages required: 3.3V, 2.5V, 1.5V.