參數(shù)資料
型號(hào)： PPC440GP-3RC333C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 440GP Embedded Processor
中文描述： 32-BIT, 333 MHz, RISC PROCESSOR, CBGA552
封裝： 25 X 25 MM, ROHS COMPLIANT, CERAMIC, BGA-552
文件頁數(shù)： 76/83頁
文件大?。?/td> 773K
代理商： PPC440GP-3RC333C
440GP – Power PC 440GP Embedded Processor
76
AMCC
Revision 1.07 – October 4, 2007
Data Sheet
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a
slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the eight DQS signals be matched.
I/O Timing—DDR SDRAM T
SIN
and T
DIN
Notes:
1. T
SIN
= Delay from DQS at package pin to C on Stage 1 FF.
2. T
DIN
= Delay from data at package pin to D on Stage 1 FF.
3. The time values for T
SIN
include 1/4 of a cycle at the indicated clock speed.
Clock Speed (MHz)
Signal Name
T
SIN
(ns)
minimum
T
SIN
(ns)
maximum
Signal Name
T
DIN
(ns)
minimum
T
DIN
(ns)
maximum
133
DQS0
2.775
3.775
MemData00:07
1.0
2.0
133
DQS1
2.775
3.775
MemData08:15
1.0
2.0
133
DQS2
2.775
3.775
MemData16:23
1.0
2.0
133
DQS3
2.775
3.775
MemData24:31
1.0
2.0
133
DQS4
2.775
3.775
MemData32:39
1.0
2.0
133
DQS5
2.775
3.775
MemData40:47
1.0
2.0
133
DQS6
2.775
3.775
MemData48:55
1.0
2.0
133
DQS7
2.775
3.775
MemData56:63
1.0
2.0
133
DQS8
2.775
3.775
ECC0:7
1.0
2.0
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