參數(shù)資料
型號(hào): PPC440GP-3CC500C
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: Power PC 440GP Embedded Processor
中文描述: 32-BIT, 500 MHz, RISC PROCESSOR, CBGA552
封裝: 25 X 25 MM, CERAMIC, BGA-552
文件頁(yè)數(shù): 58/83頁(yè)
文件大?。?/td> 773K
代理商: PPC440GP-3CC500C
440GP – Power PC 440GP Embedded Processor
58
AMCC
Revision 1.07 – October 4, 2007
Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
Logic Supply Voltage
V
DD
+1.7
+1.8
+1.9
V
4
I/O Supply Voltage
OV
DD
+3.0
+3.3
+3.6
V
4
DDR SDRAM Supply Voltage (DDR clock up to 166MHz)
SV
DD
+2.3
+2.5
+2.7
V
4
PLL Supply Voltages
AxV
DD
+1.65
+1.8
+1.95
V
3
DDR SDRAM Reference Voltage
SV
REF
+1.15
+1.25
+1.35
V
3
Input Logic High (2.5V SSTL)
V
IH
SV
REF
+0.18
SV
DD
+0.3
V
2
Input Logic High (3.3V PCI-X)
0.5OV
DD
OV
DD
+0.5
V
1
Input Logic High (3.3V LVTTL, 5V tolerant receiver)
+2.0
+5.5
V
Input Logic Low (2.5V SSTL)
V
IL
-0.3
SV
REF
-0.18
V
Input Logic Low (3.3V PCI-X)
-0.5
0.35OV
DD
V
1
Input Logic Low (3.3V LVTTL, 5V tolerant receiver)
0
+0.8
V
Output Logic High (2.5V SSTL)
V
OH
+1.95
SV
DD
V
Output Logic High (3.3V PCI-X)
0.9OV
DD
OV
DD
V
1
Output Logic High (3.3V LVTTL, 5V tolerant receiver)
+2.4
OV
DD
V
Output Logic Low (2.5V SSTL)
V
OL
0
0.55
V
Output Logic Low (3.3V PCI-X)
0.1OV
DD
V
1
Output Logic Low (3.3V LVTTL, 5V tolerant receiver)
0
+0.4
V
Input Leakage Current (No pull-up or pull-down)
I
IL1
0
0
μ
A
Input Leakage Current for Pull-Down
I
IL2
0 (LPDL)
200 (MPUL)
μ
A
5
Input Leakage Current for Pull-Up
I
IL3
-150 (LPDL)
0 (MPUL)
μ
A
5
Input Max Allowable Overshoot (3.3V LVTTL, 5V tolerant
receiver)
V
IMAO
+5.5
V
Input Max Allowable Undershoot (3.3V LVTTL, 5V tolerant
receiver)
V
IMAU
-0.6
V
Output Max Allowable Overshoot (3.3V LVTTL, 5V tolerant
receiver)
V
OMAO
+5.5
V
Output Max Allowable Undershoot (3.3V LVTTL,
5V tolerant receiver)
V
OMAU3
-0.6
V
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