- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368096 > PPC440GP-3CC400C (APPLIEDMICRO INC) Power PC 440GP Embedded Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | PPC440GP-3CC400C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Power PC 440GP Embedded Processor |
| 中文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA552 |
| 封裝： | 25 X 25 MM, CERAMIC, BGA-552 |
| 文件頁(yè)數(shù)： | 80/83頁(yè) |
| 文件大小： | 773K |
| 代理商： | PPC440GP-3CC400C |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)當(dāng)前第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)
440GP – Power PC 440GP Embedded Processor
80
AMCC
Revision 1.07 – October 4, 2007
Data Sheet
Initialization
The PPC440GP provides the option for setting initial parameters based on default values or by reading them from
a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered
by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440GP start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. They are used for strap functions only during reset. Following
reset they are used for normal functions.
The following table lists the strapping pins along with their functions and strapping options:
Serial EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device
connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440GP
sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SYS0and SYS1 registers
accordingly. Otherwise, the default values set in the STRP0 and STRP1 registers are used for initialization.
The initialization settings and their default values are covered in detail in the
PowerPC 440GP Embedded
Processor User’s Manual
.
Strapping Pin Assignments
Function
Option
Ball Strapping
V24
(UART0_DCD)
Bootstrap controller
Disabled
0
Enabled
1
V02
(UART0_DSR)
IIC0 slave address that will respond with boot data
0x54
0
0x50
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440GP-3CC400CZ | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400E | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400EZ | Power PC 440GP Embedded Processor |
| PPC440GP-3CC466C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC466CZ | Power PC 440GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440GP-3CC400CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 440GP Embedded Processor |
| PPC440GP-3CC400E | 制造商:AppliedMicro 功能描述:MPU 440GP RISC 32-Bit/64-Bit 0.18um 400MHz 3.3V 552-Pin CBGA Tray |
| PPC440GP-3CC400EZ | 制造商:AppliedMicro 功能描述:MPU 440GP RISC 32-Bit/64-Bit 0.18um 400MHz 3.3V 552-Pin CBGA T/R |
| PPC440GP-3CC466C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 440GP Embedded Processor |
| PPC440GP-3CC466CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 440GP Embedded Processor |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。