參數(shù)資料
型號： PPC405GPR-3JB333
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 405GPr Embedded Processor
中文描述： 32-BIT, 333.33 MHz, RISC PROCESSOR, PBGA456
封裝： 35 X 35 MM, LEAD FREE, PLASTIC, EBGA-456
文件頁數(shù)： 51/57頁
文件大?。?/td> 614K
代理商： PPC405GPR-3JB333
405GPr – Power PC 405GPr Embedded Processor
AMCC
51
Revision 2.04 – September 7, 2007
Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to
enable default initial conditions prior to PPC405GPr start-up. The actual capture instant is the nearest SysClk edge
before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k
Ω
to +3.3V or 10k
Ω
to
+5V. The recommended pull-down is 1K
Ω
to GND. These pins are use for strap functions only during reset. They
are used for other signals during normal operation. The following tables list the strapping pins along with their
functions and strapping options. The signal names assigned to the pins for normal operation follow the pin
number.
The PPC405GPr can be used as a replacement for the PPC405GP. When the PPC405GPr is used for this
purpose, it should be strapped to operate in the PPC405GPr Legacy Mode. This option is selected by strapping
ball D20 (GPIO24) low (0). If Legacy Mode is selected, the “PPC405GPr Legacy Mode Strapping Pin Assignments”
table should be used to determine the strapping options. To operate the chip as a PPC405GPr, strap D20
(GPIO24) high (1) and use “PPC405GPr New Mode Strapping Pin Assignments” on page 53 to determine the
strapping options.
PPC405GPr Legacy Mode Strapping Pin Assignments
(Sheet 1 of 2)
Function
Option
Ball Strapping
AF2
UART0_DTR
PLL Tuning
1
for 6
≤
M
≤
7 use choice 3
for 7 < M
≤
12 use choice 5
for 12 < M
≤
32 use choice 6
AF3
UART0_Tx
0
0
0
0
1
1
1
1
D16
DMAAck0
0
0
1
1
B14
DMAAck2
0
0
1
1
P25
EMCTxD3
0
0
1
1
AD16
UART0_RTS
0
1
0
1
0
1
0
1
Choice 1; TUNE[9:0] = 1010111100
Choice 2; TUNE[9:0] = 0100111000
Choice 3; TUNE[9:0] = 0100110110
Choice 4; TUNE[9:0] = 0100111100
Choice 5; TUNE[9:0] = 0100111000
Choice 6; TUNE[9:0] = 1000111100
Choice 7; TUNE[9:0] = 1000111110
Choice 8; TUNE[9:0] = 1011111110
0
0
1
1
0
0
1
1
PLL Forward Divider
2
B15
DMAAck1
0
1
0
1
C12
DMAAck3
0
1
0
1
L24
EMCTxD2
0
1
0
1
Bypass mode
Divide by 3
Divide by 4
Divide by 6
PLL Feedback Divider
2
Divide by 1
Divide by 2
Divide by 3
Divide by 4
PLB Divider from CPU
2
Divide by 1
Divide by 2
Divide by 3
Divide by 4
相關(guān)PDF資料
PDF描述
PPC405GPR-3JB333Z Power PC 405GPr Embedded Processor
PPC405GPR-3JB400 Power PC 405GPr Embedded Processor
PPC405GPR-3JB400Z Power PC 405GPr Embedded Processor
PPC405GPR-3KB266 Power PC 405GPr Embedded Processor
PPC405GPR-3KB266Z Power PC 405GPr Embedded Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405GPR-3JB333Z 制造商:AppliedMicro 功能描述:MPU 405GPr RISC 32-Bit 0.18um 333MHz 3.3V 456-Pin EBGA T/R
PPC405GPR-3JB400 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GPr Embedded Processor
PPC405GPR-3JB400Z 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GPr Embedded Processor
PPC405GPR-3KB266 制造商:AppliedMicro 功能描述:MPU 405GPr RISC 32-Bit 0.18um 266MHz 3.3V 456-Pin EBGA Tray 制造商:AMCC 功能描述:MPU 405GPR RISC 32BIT 0.18UM 266MHZ 3.3V 456PIN EBGA - Trays 制造商:AMCC 功能描述:AMCPPC405GPR-3KB266 "32BIT PPC CORE, UP 制造商:Applied Micro Circuits Corporation 功能描述:MPU 405GPr RISC 32-Bit 0.18um 266MHz 3.3V 456-Pin EBGA Tray
PPC405GPR-3KB266Z 制造商:AppliedMicro 功能描述:MPU 405GPr RISC 32-Bit 0.18um 266MHz 3.3V 456-Pin EBGA T/R
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